One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel.

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.

The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (53) with ion doping process; the method implements the patterning process to the bottom gate isolation layer (31) and the top gate isolation layer (32) at the same time with one photo process; the method manufactures the first top gate (71), the first source (81), the first drain (82), the second top gate (72), the second source (83), the second drain (84) at the same time with one photo process; the method implements patterning process to the flat layer (9), the passivation layer (8) and the top gate isolation layer (32) at the same time with one photo process, to reduce the number of the photo processes to five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height H.sub.b, which is less than of a height H.sub.a of the separation plug.