In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device comprises: a semiconductor substrate with an active area defined by a plurality of isolation features; a gate stack extending across the active area onto portions of the isolation features, wherein the gate stack comprising a gate dielectric layer on the active area and the portions of the isolation features, and a gate electrode on the gate dielectric layer; and a protective seal comprising a vertical portion lining sidewalls of the gate stack and a horizontal portion extending onto a top surface of the isolation features, wherein the horizontal portion surrounding portions of the gate stack outside the active area in a top view.

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

The present disclosure relates to the field of liquid crystal display, and provides a method for manufacturing a TFT and the TFT thereof. The TFT includes: a base substrate; a gate electrode with a three-dimensional structure formed on the base substrate; a gate insulating layer for completely covering a top face and two side faces of the gate electrode; a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer; a buffer layer for covering a top face and two side faces of the semiconductor layer at two ends of the semiconductor layer; and source and drain electrodes for completely covering a top face and two side faces of the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure.

Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

A voltage switchable coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A chrome oxide layer is formed on the cobalt by MBE at room at UHV at room temperature. There was thin cobalt oxide interface between the chrome oxide and the cobalt. Other magnetic materials may be employed. A few ML field of graphene is deposited on the chrome oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.