Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

The present invention relates to a method for forming nano-gaps in graphene. The method may include applying a voltage across a region of graphene such that a nano-gap which extends across the entire width of the graphene is formed, wherein the region across which the voltage is applied may include a point which is the narrowest in the region.

Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

A method for adjusting a qubit includes measuring a qubit characteristic of a qubit device and computing a modification to correct the qubit characteristic. A geometry of a shunt capacitor is adjusted using a laser direct write process. The qubit characteristic is verified.

Provided is an electronic element that functions as a switch or memory without using metal nanoparticle. The electronic element includes: one electrode 5A and an other electrode 5B arranged to have a nanogap therebetween; and halide ion 6 provided between the electrodes 5A and 5B; and on one of the electrodes.

A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

A charge-sensing semiconductor device is provided. The device comprises a substrate body, a source formed along a first sidewall of the substrate body, and a drain formed along a second sidewall of the substrate body. A first and a second delta layer are disposed on the substrate body and are separated by a gap. The first delta layer is in contact with the source and the second delta layer is in contact with the drain. A cap is disposed over the first and second delta layers. The first and second delta layers are embedded between the substrate body and the cap. The first and second delta layers are formed by thin layers of phosphorus, and the substrate body and the cap are formed of a semiconductor material.

The disclosed semiconductor structure includes: a substrate and a data line on the substrate, the data line extends along a first direction; the first transistor and the second transistor located on the first transistor's side away from the data line; each of the first transistor and the second transistor includes: a semiconductor column, the semiconductor column is located on a part of the top surface of the data line and extends along the third direction; an isolation structure inside the semiconductor column; along the second direction, the thickness of the isolation structure in different regions in the third direction is different, and the isolation structure runs through the semiconductor columns, and two of the first, the second and the third directions intersect each other. This improves the sensitivity of the second transistor to the change in current in the first transistor while reducing the leakage current in the first transistor.