Provided in one embodiment is a device, comprising: a substrate; and a layer disposed over the substrate, wherein the layer comprises a monolayer of crystals comprising a Group IV element.

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Embodiments of the present disclosure are directed to a side-gated fin field effect transistor configured as a scanning single electron transistor. In a non-limiting embodiment, a scanning single electron transistor includes a fin formed over a substrate. A source gate is formed over a first portion of the substrate that extends over a sidewall of the fin. A drain gate is formed over a second portion of the substrate that extends over the sidewall of the fin. A plunger gate is formed over a third portion of the substrate that extends over the sidewall of the fin. The plunger gate is positioned between the source gate and the drain gate. The plunger gate is etched back from a topmost surface of the fin such that a quantum dot formed in the fin is not screened by metallic materials in the plunger gate.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Quantum device formed from a substrate, the substrate being covered: with at least one semiconductor region forming a quantum dot, a detection structure with Coulomb blockade for detecting a state of charge of the quantum dot, said detection structure with Coulomb blockade including a detection island disposed above and facing the quantum dot and able to be coupled to the quantum dot by electrostatic coupling, said detection structure furthermore including at least one first tunnel junction between said detection island and a first gate block, the first gate block being juxtaposed with said detection island.

The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

Engineered quantum processing elements are disclosed. The engineered quantum processing element includes a dopant dot embedded in a semiconductor substrate. A dielectric material forms an interface with the semiconductor substrate. The dopant dot includes a plurality of dopant atoms and one or more electrons/holes confined within the dopant dot. The geometrical configuration of the plurality of dopant atoms with respect to the semiconductor substrate is engineered to achieve optimal linear hyperfine Stark coefficients. Further, aspects of the present disclosure are directed to methods of fabricating such engineered quantum processing elements.

The invention provides a spin qubit-type semiconductor device capable of achieving both high-speed spin manipulation and high integration, and an integrated circuit for the spin qubit-type semiconductor device. The spin qubit-type semiconductor device includes a body comprised of at least one of a semiconductor layer itself formed with a quantum dot and a structural portion arranged around the semiconductor layer, a gate electrode arranged at a position on the semiconductor layer, which faces the quantum dot, at least one micro magnet wholly or partly embedded in the body so that a first position condition in which the micro magnet is at a position near the quantum dot, a second position condition in which the position of a lower end of the micro magnet is located below the gate electrode, and a third position condition in which when viewed from above the body, the micro magnet is arranged at a position having no rotational symmetry with the quantum dot as the center of rotation are satisfied, and a static magnetic field applying unit capable of applying a static magnetic field to the quantum dot and the micro magnet.

A structure for cooling a component of a quantum device by circulating a given current between a first contact element with the component and a second contact element with the component, the first contact element comprising at least one given superconducting metal material, in particular at a given temperature less than 2K, and being in contact by a first end with a first semiconductor portion of said component so as to form with the first semiconductor portion at least one cooling tunnel junction.

A method for making a qubit device comprising a chiral nanocrystal includes forming a gate electrode on a non-conducting substrate, forming an insulating layer over the back gate electrode, immobilizing a bottom face of a semiconductor nanocrystal onto the insulating layer, and placing two or more electrodes on, or in apposition to, a top face of the semiconductor nanocrystal.