A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A semiconductor structure includes a substrate and a memory element. The memory element is disposed on the substrate and includes a floating gate, a tunnel dielectric layer, a control gate structure, an inter-gate oxide layer, an erase gate, and a word line. The floating gate is disposed on the substrate. The tunnel dielectric layer is disposed between the floating gate and the substrate. The control gate structure is disposed on the floating gate. The control gate structure includes a high-k dielectric layer and a metal gate, and a width of a top portion of the control gate structure is greater than a width of a bottom portion of the control gate structure. The inter-gate oxide layer is disposed between the floating gate and the control gate structure. The erase gate is disposed on one side of the floating gate. The word line is disposed on the other side of the floating gate. A manufacturing method of a semiconductor structure is also provided.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a tunneling dielectric layer disposed on the substrate, a plurality of transistor structures disposed on the tunneling dielectric layer. Each transistor structure includes a floating gate, an inter-gate dielectric layer, and a control gate sequentially disposed on the tunneling layer. In a cross-sectional view along a first direction, the control gate is disposed between opposing sidewalls of the floating gate.

A method of manufacturing a non-volatile memory device includes steps of forming an assist gate on the substrate, the assist gate including two sidewalls opposite to each other, forming a patterned conductive layer on the substrate, the patterned conductive layer covering at least one of the two sidewalls of the assist gate, forming a spacer on a top surface of the patterned conductive layer, where a portion of the top surface of the patterned conductive layer is covered by the spacer, etching the patterned conductive layer using the spacer as an etch mask to form a floating gate, the floating gate including two first top edges opposite to each other, and forming an upper gate covering the assist gate and the floating gate, where at least one of the two first top edges of the floating gate is embedded in the upper gate.

A non-volatile memory device includes multiple memory cell, and the memory cell includes an assist gate structure, a tunneling dielectric layer, a floating gate, an upper gate and a middle structure. The floating gate is disposed on the tunneling dielectric layer and includes two first top edges opposite each other, two first sidewalls connected to the two top edges respectively, two second sidewalls arranged along a second direction. An upper gate structure covers the assist gate structure and the floating gate, where at least one of the two first top edges of the floating gate is embedded in the upper gate structure. A middle structure covers one of the two first sidewalls of the floating gate and opposite the assist gate structure. The floating gate is disposed between the middle structure and the assist gate structure, and the middle structure is an insulating structure or a control gate structure.

Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. ALEFTis a device that reduces the cost of manufacture while allowing scaling and improving device performance. A requirements of IoT devices is the ability to store data on chips using integratable memory. FCNVM-ALEFT is an integratable non-volatile memory device with a protected floating gate that is integratable with the ALEFT devices with minimum additional processing. ALEFT devices integrated with FCNVM-ALEFT is a suitable technology combination for the IoT devices.

A method for forming a semiconductor memory device is disclosed. A substrate is provided. A pair of floating gates are formed on the substrate. A recessed region is formed in the substrate between the floating gates, wherein an upper surface of the recessed region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates. A source line doped region is formed in the recessed region. An erase gate is formed between the floating gates and on the recessed region, and a word line is formed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate. A bit line doped region is formed in the substrate and adjacent to the word line.

A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.