A non-volatile memory (NVM) bit cell is disclosed. The NVM bit cell includes a control gate, a state transistor, and an access transistor coupled in series with the state transistor. The control gate includes a floating terminal formed by a first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control-gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control-gate dielectric layer includes a high-K dielectric layer. The state transistor comprises a floating-gate terminal formed by the first polysilicon layer and coupled to the floating terminal of the control gate. The state transistor further comprises a tunnel oxide layer formed between the first polysilicon layer and an active area of the state transistor.