Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding adjacent memory transistor.

A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.

A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.