A semiconductor memory device includes a cell area and a peripheral area, a base insulating layer including opposed first front and rear surfaces in the cell area, a first semiconductor substrate including opposed second front and rear surfaces in the peripheral area, an active pattern on the first front surface, a first conductive line extending in a first direction on a side of the active pattern, a capacitor structure on the active pattern, a first circuit element on the second front surface, and a second conductive line extending in a second direction intersecting the first direction on the first rear surface and the second rear surface. The active pattern extends in a vertical direction intersecting the first direction and the second direction to electrically connect the second conductive line to the capacitor structure.

Semiconductor memory devices may include a cell substrate including a cell array region, first and second extension regions and a through region, a first mold structure including first gate electrodes stacked in a stepwise manner, a first interlayer insulating layer extending conformally on the first gate electrodes on the second extension region, a second interlayer insulating layer on the first interlayer insulating layer, a second mold structure including second gate electrodes on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner, a channel structure in the first and second mold structures on the cell array region, a first cell contact structure in the first mold structure on the second extension region, and a second cell contact structure in the first and second mold structures on the first extension region. The first and second interlayer insulating layers may have different impurity concentrations.

According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.

A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.

A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer. The bit lines are positioned under the memory layers.

A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.