Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a plurality of memory blocks in a plan view and at least one stabilization structure extending laterally to separate adjacent ones of the memory blocks in the plan view. Each of the memory blocks includes a memory stack including vertically interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending vertically through the memory stack. The stabilization structure includes a dielectric stack including vertically interleaved second dielectric layers and the first dielectric layers.

A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

According to one embodiment, a semiconductor storage device includes a stacked structure in which a plurality of conductive layers is stacked in a stacking direction via an insulating layer, a plurality of pillars extending in the stacking direction in the stacked structure and including a memory cell formed at an intersection between at least a part of the plurality of conductive layers and at least a part of the plurality of pillars, a plurality of first contacts arranged in the stacked structure, each of the first contacts reaching a different depth in the stacked structure and being connected to a conductive layer in a different layer among the plurality of conductive layers, and a plurality of second contacts arranged in the stacked structure separately from the plurality of first contacts, each of the second contacts being connected to a conductive layer identical to the conductive layer to which corresponding one of the plurality of first contacts is connected.

A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.

A semiconductor memory device is disclosed. The device may include an electrode structure including electrodes, the electrodes stacked on a substrate, a source semiconductor layer between the substrate and the electrode structure, and a vertical channel structure penetrating the electrode structure. The vertical channel structure includes a vertical insulating pattern, a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor pattern and the electrode structure; and a barrier pattern spaced apart from the electrode structure with the vertical semiconductor pattern interposed between the barrier pattern and the electrode structure. The vertical semiconductor pattern comprises a recess region, the source semiconductor layer extending in the recess region. The barrier pattern includes an insulating layer including carbon.

A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.