A method of manufacturing a thin-film transistor substrate that includes a thin-film transistor having a semiconductor layer, includes: forming a CuMn alloy film (third conductive film) above a substrate; forming a first silicon oxide film (first insulation film) on the CuMn alloy film at a first temperature; forming an aluminum oxide film (second insulation film) on the first silicon oxide film; and forming a second silicon oxide film (third insulation film) on the aluminum oxide film at a second temperature higher than the first temperature.

A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

In various embodiments, a method of processing a semiconductor device may include providing a semiconductor device comprising a contact pad and a polymer layer; and subjecting at least a part of the contact pad and the polymer layer to a plasma comprising ammonia.

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

A super-semiconductor (SSC), semiconductor devices including the SSC, and methods for making the SSC. The SSC includes a bimetallic nanostructured array having a substrate and a nanoshell array disposed on the substrate. The nanoshell array is defined by a plurality of non-close-packed, non-conductive, core bodies disposed on the substrate, a first metal layer disposed on the non-conductive core bodies and on the substrate in areas located between adjacent non-conductive core-bodies, and at least a second metal layer disposed on the first metal layer, wherein the second metal is different than the first metal. The bimetallic nanostructured array exhibits p-type or n-type metal conductivity above a transition temperature, and in embodiments, exhibits resistivity in a range of 10.sup.8-10.sup.7 ohm*m at a temperature of 300K+/40K.

The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

A semiconductor device includes first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region includes fifth and sixth insulating portion. The fourth electrode is arranged with the first semiconductor region and the third electrode. The second insulating part is located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode. The fourth semiconductor region is located under the sixth insulating portion.

A semiconductor device includes a substrate, a source electrode extending, a drain electrode, a first gate electrode extending in a first direction and provided between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on the substrate in the first direction of the first gate electrode between the source electrode and the drain electrode, a gate pad provided so as to interpose the first gate electrode between the second gate electrode and the gate pad and electrically connected to the first gate electrode, a gate wiring provided above the source electrode and electrically connecting the gate pad and the second gate electrode, and a guard metal layer provided between the gate wiring and the drain electrode, at least a part of the guard metal layer being provided above the source electrode and electrically connected to the source electrode.