A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.

The semiconductor substrate has an active region, a termination regions surrounding a periphery of the active region, and a transition region between the active region and the termination region. The transition region has a portion that overlaps an outer peripheral portion of the active region by a predetermined width. The portion of the transition region includes at least one pair of one of the n-type column regions in the active region and an adjacent one of the p-type column regions in the active region. The parallel pn layer exhibits doping concentration distributions of n-type and p-type in each of which the doping concentration is relatively high in a center portion of the active region, progressively decreases in the transition region in a direction from the active region to the edge termination region, and is relatively high in the termination region.

A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region, and an outer cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region.

According to one embodiment, a semiconductor device includes a first electrode, a first conductive member, a first semiconductor region, and a second semiconductor region. The first semiconductor region is of a first conductivity type and is provided between the first electrode and the first conductive member. The first semiconductor region includes first to third partial regions. The first semiconductor region and the first conductive member forms a Schottky junction, The second semiconductor region is of a second conductivity type. The second semiconductor region includes a plurality of first portions extending along a first direction, a plurality of second portions extending along a second direction, and a third portion.

A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

A semiconductor device includes a first conductivity type semiconductor layer having a first and second surfaces, device and outer regions, a channel region of a second conductivity type in a surface layer portion of the first surface in the device region, an emitter region of a first conductivity type in a surface layer portion of the channel region, a gate electrode at the first surface in the device region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type in a surface layer portion of the second surface in the device region, an inner cathode region of a first conductivity type in the surface layer portion of the second surface in the device region, and an outer cathode region of a first conductivity type in the surface layer portion of the second surface in the outer region.

A semiconductor device includes an active region comprising first and second mesa stripes and a trench between the mesa stripes. The trench has a first width between the first and second mesa stripes near a central portion of the first and second mesa stripes and a second width between the first and second mesa stripes near end portions of the first and second mesa stripes. The second width is less than the first width.

A semiconductor device includes: a high-concentration layer of a first conductivity-type provided on a drift layer of the first conductivity-type; a buried layer of a second conductivity-type provided in the high-concentration layer; an injection regulation region of the second conductivity-type provided on the high-concentration layer; a high-concentration region of the second conductivity-type provided inside the injection regulation region; a carrier supply region of the first conductivity-type provided at an upper part of the injection regulation region; and an insulated gate structure provided inside a trench, wherein a ratio of the impurity concentration of the injection regulation region to an impurity concentration of an upper part of the high-concentration layer is 0.5 or greater and 2 or smaller.