A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function .sub.MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or flare the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function .sub.MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

An integrated MOSFET-JFET device made from a Silicon-Carbide (SiC) wafer has N+ source, P body diode, and upper N regions that form vertical MOSFETs on the sidewalls of polysilicon gates. An N substrate under the upper N region forms a drift region that is pinched by the JFET to limit saturation current. Trenches are formed between MOSFETs. JFETs are formed by doping the bottom and sidewalls of the trenches to form P+ taps to the N substrate. P islands within the N substrate are formed underneath the P+ taps. These P islands are wider near the surface but are successively narrower with increased vertical spacing deeper into the N substrate. This P-island tapering provides a tapered shape to the JFET depletion region that pinches the MOSFET drift region in the N substrate to limit saturation current and yet reduce linear-region ON resistance.

A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line, and a second clock signal line in a peripheral region; a first portion and a second portion of a first connection wire of the display substrate are connected to a first gate electrode of a first control transistor of the shift register unit; an orthographic projection of the first portion on the base substrate is on a side of an orthographic projection of an active layer of the first control transistor on the base substrate away from a display region; and an orthographic projection of the second portion on the base substrate is on a side of the orthographic projection of the active layer of the first control transistor on the base substrate close to the display region.

A semiconductor device comprises a plurality of gate structures stacked with a plurality of core channel layers comprising a first semiconductor material, and a plurality of cladding channel layers disposed around the plurality of gate structures and comprising a second semiconductor material different from the first semiconductor material. A source/drain region is disposed on a side of the plurality of gate structures and the plurality of core channel layers. Respective ones of a plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel layers and the source/drain region.

A method for forming a semiconductor structure includes: providing a substrate, in which a gate structure is formed on the substrate; forming first side walls covering side surfaces of the gate structure, in which the first side walls have a first preset thickness in a direction parallel to a plane of the substrate; performing first ion implantation on the substrate on both sides of the gate structure exposed to the first side walls; removing a part of the first side walls to form second side walls, in which the second side walls have a second preset thickness in the direction parallel to the plane of the substrate; and performing second ion implantation on the substrate on both sides of the gate structure, in which doping types of the first ion implantation and the second ion implantation are different.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BV.sub.DSS and ON-state breakdown voltage BV.sub.ON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds V.sub.TH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local V.sub.TH and thus decreased current leakage. P hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

An object of the present disclosure is to achieve a stable current sensing operation and suppress decrease in main current at a low temperature of 0 C. or less in a silicon carbide semiconductor device. An SiC-MOSFET includes: a main cell outputting main current; and a sense cell outputting sense current proportional to the main current, wherein temperature dependent properties of the main current differ in accordance with threshold voltage of the main cell, temperature dependent properties of the sense current differ in accordance with threshold voltage of the sense cell, the threshold voltage of the main cell is smaller than the threshold voltage of the sense cell, and in a temperature of 0 C. or less, an inclination of the temperature dependent properties of the main current is smaller than an inclination of the temperature dependent properties of the sense current.

A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films.