Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

An imaging element includes a plurality of pixels that are two-dimensionally arranged and each have a light receiving part including a photoelectric conversion element and a light collecting part that collects incident light toward the light receiving part. Each of the light collecting parts in the plurality of pixels includes an optical functional layer having, in a surface, a specific projection and depression structure depending on the pixel position.

An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.

An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof and a display apparatus. The array substrate includes a base substrate, wherein, the base substrate is provided with a bonding region; a bonding pad and a first bonding lead connected with the bonding pad and extending to an edge of the base substrate are provided in the bonding region, and one or more metal patterns are arranged above the first bonding lead, the one or more metal patterns crossing over the first bonding lead and being insulated from the first bonding lead.

An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.

An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

Methods of measuring and calibrating the gain of a CCD imaging system are described. Charge injectors may be present on either side of an image sensor array that provide test charges to respective calibration VCCDs. Test charges may be transferred to upper and lower HCCDs during quad-output read out or to only the lower HCCD during dual-output or single-output read out. In each quadrant of the imaging system, test charges may be transferred to an EMCCD output or to a non-EMCCD output via a charge switch based on the magnitude of the test charges. The gains of all EMCCD outputs and non-EMCCD outputs in the imaging system may be calibrated against one another by adjusting the gain at each output when a discrepancy is detected between any two outputs.

A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.