A method for fabricating semiconductor devices is disclosed herein. The method includes forming a first gate region extending into a substrate and having at least a vertical portion of a first U-shape, where the first gate region has a first conductive type. The method includes forming a channel region extending into the substrate and having a second U-shape surrounded by the first U-shape, where the channel region has a second conductive type. The method includes forming a pair of first epitaxial structures coupled to end portions of the first gate region, respectively, where the first epitaxial structures have the first conductive type. The method includes forming a pair of second epitaxial structures coupled to end portions of the channel region, respectively, where the second epitaxial structures have the second conductive type. The method includes forming a third epitaxial structure having the first conductive type and surrounded by the second U-shape.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.

A vertical junction field effect transistor includes a trench structure laterally arranged between mesa regions along a first lateral direction. The trench structure extends into a semiconductor body from a first surface of the semiconductor body. Each of the mesa regions includes a mesa channel region of a first conductivity type. The vertical junction field effect transistor further includes a gate region of a second conductivity type. The gate region adjoins at least part of opposite sidewalls of the trench structure and to a bottom side of the trench structure. The trench structure includes a silicon layer adjoining the gate region at the bottom side of the trench structure. A first thickness of the gate region at the bottom side of the trench structure is larger than a second thickness of the gate region at each of the opposite sidewalls of the trench structure.

A transistor that may include a drift layer formed on a substrate. A well implant layer formed within the drift layer wherein the well implant layer has a first gap. A gate implant layer formed within the drift layer and partially over the well implant layer wherein the gate implant layer has a second gap. A source implant layer formed within the drift layer and within the second gap of the gate implant layer. A plurality of gate contacts operatively connected to the gate implant layer. A source contact operatively connected to the source implant layer.

A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.

A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

Methods to fabricate a semiconductor device, the method including: forming a first level, the first level including a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers, where each transistor of the plurality of transistors includes a single crystal channel, and where the plurality of first metal layers include interconnections between the transistors of the plurality of transistors; thinning the single crystal silicon layer to a thickness of less than two microns; forming a second level, the second level including a plurality of second metal layers, where the second level is disposed underneath the first level; and forming a connection path between at least one of the transistors to at least one of the plurality of second metal layers, where the connective path includes at least one via disposed through at least the single crystal silicon layer.

Methods to fabricate a semiconductor device, the method including: forming a first level, the first level including a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers, where each transistor of the plurality of transistors includes a single crystal channel, and where the plurality of first metal layers include interconnections between the transistors of the plurality of transistors; thinning the single crystal silicon layer to a thickness of less than two microns; forming a second level, the second level including a plurality of second metal layers, where the second level is disposed underneath the first level; and forming a connection path between at least one of the transistors to at least one of the plurality of second metal layers, where the connective path includes at least one via disposed through at least the single crystal silicon layer.