A source layer is provided on a first p-type layer made of a nitride-based semiconductor, and includes a semiconductor region including electrons as carriers. A drain layer faces the source layer in a first direction on the first p-type layer with a gap being provided therebetween, and includes a semiconductor region including electrons as carriers. A channel structure is provided between the source layer and the drain layer on the first p-type layer, in which a channel region and a gate region are alternately disposed in a second direction perpendicular to the first direction. A channel layer included in the channel structure forms at least a part of the channel region, and is made of a nitride-based semiconductor. A gate layer included in the channel structure forms at least a part of the gate region, and electrically connects a gate electrode and the first p-type layer.

A source layer is provided on a first p-type layer made of a nitride-based semiconductor, and includes a semiconductor region including electrons as carriers. A drain layer faces the source layer in a first direction on the first p-type layer with a gap being provided therebetween, and includes a semiconductor region including electrons as carriers. A channel structure is provided between the source layer and the drain layer on the first p-type layer, in which a channel region and a gate region are alternately disposed in a second direction perpendicular to the first direction. A channel layer included in the channel structure forms at least a part of the channel region, and is made of a nitride-based semiconductor. A gate layer included in the channel structure forms at least a part of the gate region, and electrically connects a gate electrode and the first p-type layer.

A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

A field-effect transistor with a shielded source, and a method of making the same. A volume of semiconductor material includes first and second vertically spaced ends and first and second laterally spaced sides. First and second laterally spaced gates are provided in the volume of semiconductor material. A source is located at the first end between the first and second gates, a drain is provided, and a channel extends therebetween. The first gate includes a lower first gate portion spaced below and extending beneath the source so as to create a turn in the channel around the lower first gate portion.

A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

The planar junction field-effect transistor provides enhanced channel control. A method of making such a JFET is also disclosed. A volume of semiconductor material includes a first end and a second end, a source and a first gate are located at the first end, a drain is spaced apart from the source, and a channel is provided between the source and the drain. A second gate is located between the source and drain so as to be surrounded, or buried, in a first dimension and a second dimension by the semiconductor material, and thereby divides the channel into multiple non-linear channel paths. The gates cooperatively determine the channel paths and enhance the channel control. The second gate may include an extension in a third dimension through the semiconductor material. The extension may present an exposed surface for an electrical terminal for receiving a voltage.

A transistor comprising an epi layer formed within a substrate. A junction field-effect transistor implant layer formed into the epi layer. A well implant layer formed within the junction field-effect transistor implant layer. A source implant layer formed into the junction field-effect transistor implant layer. A plurality of first gate implant layers formed into the junction field-effect transistor implant layer. A plurality of first gate contacts operatively connected to the respective first gate implant layer. A source contact operatively connected to the source implant layer. A second gate contact operatively connected to the well implant layer.

A mesa junction field-effect transistor is provided with channel engineering, and a method of making such a device is disclosed. A volume of semiconductor material includes a first end, a second end, a first side, and a second side. A channel extends between a source located at the first end and a drain. A first gate is located at the first side. A second gate is located at the second side, opposite the first gate, and includes upper and lower components located along an opposite side of the channel. The lower second gate component is spaced below and extends beneath the source, thereby creating at least two turns in the channel. The first and second gates cooperate to provide multiple control points in the non-linear channel for controlling electrical current flowing through the channel.

A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

The present invention relates to a semiconductor element and a method for manufacturing same, wherein the semiconductor element may comprise: a base element, an intermediate layer formed in at least one direction of the base element; and a metal layer formed on the intermediate layer in a direction opposite to the base element, and wherein a conductive filament may be formed inside the intermediate layer according to the application of a voltage to the intermediate layer.