A semiconductor device includes: an n.sup.+-type drain region deposited at an upper part of a p-type semiconductor base body; an n-type drift region deposited to be in contact with the n.sup.+-type drain region; an n.sup.+-type source region opposed to the n.sup.+-type drain region with the n-type drift region interposed; a p-type gate region deposited to be in contact with the n-type drift region; an interlayer insulating film covering the n-type drift region; a resistive element having a spiral-like planar shape provided inside the interlayer insulating film; a drain electrode wire connected to the n.sup.+-type drain region and one end of the resistive element; a source electrode wire connected to the n.sup.+-type source region; a gate electrode wire connected to the p-type gate region; and a potential-dividing terminal wire connected to the resistive element, wherein a gap between the source electrode wire and an outermost circumference of the resistive element is constant.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.

A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.

A semiconductor device that includes at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer. Composition grading along a predetermined axis and changes in energy bandgap in space by compositional grading, alloy material, and effects of said any adjacent layers results in the at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer being one of an n-type layer with a density distribution of electrons or a p-type layer with a density distribution of holes, depending on design choices. The at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer is disposed on a substrate layer.

A nitride semiconductor device includes: a substrate; a drift layer, a high-resistance layer, and a first base layer above the substrate in stated order; a gate opening penetrating through the first base layer and the high-resistance layer to the drift layer; an electron transport layer and an electron supply layer covering an upper portion of the first base layer and the gate opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; an electrode opening penetrating through the electron supply layer and the electron transport layer to the first base layer; a potential fixing electrode in contact with the first base layer at a bottom part of the electrode opening; and a drain electrode below the substrate.

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.