Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.

MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5 to about 60 within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises one or more semiconductor layers, a gate on the one or more semiconductor layers, a source/drain region including a first portion in the one or more semiconductor layers and a second portion in the one or more semiconductor layers, and a defect region in the one or more semiconductor layers. The defect region is disposed adjacent to the first portion of the source/drain region.

A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

It is an object to form a buffer circuit, an inverter circuit, or the like using only n-channel TFTs including an oxide semiconductor layer. A buffer circuit, an inverter circuit, or the like is formed by combination of a first transistor in which a source electrode and a drain electrode each overlap with a gate electrode and a second transistor in which a source electrode overlaps with a gate electrode and a drain electrode does not overlap with the gate electrode. Since the second transistor has such a structure, the capacitance C.sub.p can be small, and V.sub.A can be large even in the case where the potential difference VDDVSS is small.

A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.

The present disclosure provides a vertical inverter and a semiconductor device including the vertical inverter, and the vertical inverter includes an insulation substrate, a first thin film transistor, and a second thin film transistor. By a layered arrangement of the first and second thin film transistors of the vertical inverter, more thin film transistors can be arranged within the limited space, so that the integration degree of the thin film transistors in the semiconductor device can be improved.

High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.