According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

A light-emitting device includes a plurality of pixels arranged in a substrate. Each pixel includes a light-emitting element, a driving transistor configured to supply a current to the light-emitting element, and a write transistor configured to supply a signal voltage to a gate of the driving transistor. The driving transistor has an offset structure that includes an insulator between the gate and a semiconductor region forming one of a source and a drain of the driving transistor in an orthogonal projection to a main surface of the substrate.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BV.sub.DSS and ON-state breakdown voltage BV.sub.ON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds V.sub.TH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local V.sub.TH and thus decreased current leakage. P hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.

A semiconductor device such as, for example, a gate-all-around field-effect transistor (GAAFET) device suitable for operability under higher operating voltage conditions (e.g., 1.2 volts to 3.3 volts). The semiconductor device includes a first channel that is formed in a first plane of the semiconductor device, a second channel that is formed in a second plane of the semiconductor device different from the first plane, a drain that is formed around the first channel, a gate that is formed around the second channel, and a source that is formed around the second channel.

A thin film transistor includes an active layer, first and second electrodes, and a third doped pattern. The active layer has a channel region, and a first electrode region and a second electrode region, the first electrode region has a first ion doping concentration, and the second electrode region has a second ion doping concentration. The first electrode and the second electrode are disposed on a side of the active layer in the thickness direction. The first electrode is coupled to the first electrode region, and the second electrode is coupled to the second electrode region. The third doped pattern is disposed between the first electrode and the first electrode region, and in direct contact with the first electrode and the first electrode region. The third doped pattern has a third ion doping concentration, and the third ion doping concentration is different from the first ion doping concentration.

In one aspect, a silicon-on-insulator semiconductor device includes: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; and a drift region disposed on the buried dielectric layer. An upper surface of the drift region forms a drop structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side. An upper surface of the second side is higher than a bottom surface of the first side, such that a thickness of the drift region at the second side is greater than that at the first side. The first electrode and the second electrode are configured such that a voltage applied to the second electrode is greater than a voltage applied to the first electrode when a reverse bias voltage is applied to the device.