A small-sized frequency-variable terahertz oscillator has a successive and large frequency-sweeping width even at a room temperature. The frequency-variable terahertz oscillator includes a slot antenna, a resonant tunneling diode and a varactor diode arranged parallel to each other along the slot antenna. The frequency-variable terahertz oscillator oscillates in a terahertz frequency range when the resonant tunneling diode and the varactor diode are separately applied with a direct voltage.

The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

An electronic device in the form a two-dimensional array of nanopillars extending generally normal to a substrate is provided. The nanopillars are made from a paraelectric or superparaelectric material. In addition, a linear dielectric medium is located between individual nanopillars. A two-dimensional array of paraelectric or superparaelectric nanopillars and a linear dielectric medium form the effective dielectric medium of a paraelectric or superparaelectric varactor. In some instances, the nanopillars are cylindrical nanopillars that have an average diameter and/or average height/length between 1-300 nanometers. In other instances, the nanopillars are quasi-nanoparticles that form self-aligned nano-junctions. In addition, each of the nanopillars has a single paraelectric or superparaelectric dipole domain therewithin. As such, each of the nanopillars can be void of crystallographic defects, polycrystallinity, interactions between ferroic domains, and defects due to ferroic domain walls.

Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

An integrated circuit (IC) die for electromagnetic band gap (EBG) noise suppression is provided. A power mesh and a ground mesh are stacked within a back end of line (BEOL) region overlying a semiconductor substrate, and an inductor is arranged over the power and ground meshes. The inductor comprises a plurality of inductor segments stacked upon one another and connected end to end to define a length of the inductor. A capacitor underlies the power and ground meshes, and is connected in series with the inductor. Respective terminals of the capacitor and the inductor are respectively coupled to the power and ground meshes. A method for manufacturing the IC die is also provided.

An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

A lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.

A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

A device includes a first stacked capacitor comprising a first MOS capacitance and a first MOM capacitance, the first MOS capacitance coupled to a first node, the first node configured to receive a first bias voltage, and a second stacked capacitor comprising a second MOS capacitance and a second MOM capacitance, the second MOS capacitance coupled to the first node.