The present invention provides a display panel and a display device. In the display panel, edges of multiple rows of pixel units are arranged in a step-like manner, each row of pixel units include a central pixel unit and a marginal pixel unit, each central pixel unit includes first thin film transistors each corresponding to a sub-pixel and having a first semiconductor region; each marginal pixel unit includes second thin film transistors each corresponding to a sub-pixel and having a second semiconductor region; length and width of the first semiconductor region are respectively set to be a first set length and a first set width, length and width of the second semiconductor region are respectively set to be a second set length and a second set width such that brightness of the marginal pixel unit is smaller than brightness of the central pixel unit during display.

The present application discloses a pixel structure and a display device. The pixel structure includes: a scan line having a branch structure; and a semiconductor pattern intersecting with the scan line and the branch structure. The semiconductor pattern includes: a first channel region disposed below the scan line; a second channel region disposed below the branch structure; and doping regions respectively disposed at two sides of the first channel region and at two sides of the second channel region. Wherein, the width of the second channel region is less than the width of the first channel region. The pixel structure may improve the display performance of the display screen.

A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.

The semiconductor device includes a first transistor including a first gate electrode, a second transistor including a second gate electrode electrically connected to the first gate electrode and a source electrode electrically connected to a drain electrode of the first transistor. The first transistor includes a first channel width and a first gate length. The second transistor includes a second channel width and a second gate length. A value obtained by dividing the second channel width by the second gate length is greater than or equal to a value obtained by dividing the first channel width by the first gate length.

An object is to obtain a rectifier having a small voltage drop and to reduce the fabrication cost of a converter circuit. A photoelectric transducer device including: a photoelectric transducer element; and a converter circuit stepping up or stepping down an output of the photoelectric transducer element and including a switching element and a rectifier, in which the switching element is a first oxide semiconductor transistor that is normally off and in which the rectifier is a second oxide semiconductor transistor that is diode-connected and normally on.

A display device is disclosed, which includes: a substrate having a display region; and a first thin film transistor (TFT) unit disposed on the display region and comprising: a first gate electrode disposed on the substrate; a first insulating layer disposed on the first gate electrode; a first semiconductor layer disposed on the first insulating layer, wherein the first semiconductor layer has a top surface which comprises a concave region and a non-concave region; and a first source electrode and a first drain electrode disposed on the top surface of the first semiconductor layer, wherein the first semiconductor layer has a first thickness corresponding to the concave region, and the first semiconductor layer has a second thickness corresponding to the non-concave region, wherein the second thickness is greater than the first thickness.

The present invention provides a Low Temperature Poly-silicon TFT substrate structure and a manufacture method thereof. By providing the amorphous silicon layers in the drive TFT area and the display TFT area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.

A manufacturing method of a thin film transistor array panel invention includes forming a semiconductor layer on a substrate including a display area and a peripheral area, arranging a photo mask including a first portion and a second portion having different transmittances from each other, the first portion corresponding to the display area and the second portion corresponding to the peripheral area, and patterning the semiconductor layer to form a first semiconductor disposed in the display area and a second semiconductor disposed in the peripheral area by using the photo mask, in which a thickness of the first semiconductor and a thickness of the second semiconductor are different from each other.

An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.