LOW TEMPERATURE POLY-SILICON TFT SUBSTRATE STRUCTURE AND MANUFACTURE METHOD THEREOF

Abstract

The present invention provides a Low Temperature Poly-silicon TFT substrate structure and a manufacture method thereof. By providing the amorphous silicon layers in the drive TFT area and the display TFT area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.

Claims

1. A manufacture method of a Low Temperature Poly-silicon TFT substrate structure, comprising steps of: step 1, providing a substrate, and the substrate comprises a drive TFT area and a display TFT area, and deposing a buffer layer on the substrate; step 2, deposing an amorphous silicon layer on the buffer layer, and patterning the polysilicon layer so that a thickness of the amorphous silicon layer in the display TFT area is larger than a thickness of the amorphous silicon layer in the drive TFT area; step 3, implementing an Excimer Laser Annealing process to the amorphous silicon layer to make the amorphous silicon layer to be crystallized and converted to be a polysilicon layer after an Excimer Laser Annealing pretreatment; step 4, patterning the polysilicon layer to obtain a first polysilicon section in the drive TFT area and a second polysilicon section in the display TFT area; step 5, deposing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer; step 6, deposing and patterning a first metal layer on the gate isolation layer, and forming a first gate and a second gate respectively above the first polysilicon section and the second polysilicon section and corresponding thereto; step 7, deposing an interlayer insulation layer on the gate isolation layer, the first gate and the second gate, and forming a first via and a second via in the interlayer insulation layer and the gate isolation layer respectively above the first polysilicon section and the second polysilicon section and corresponding thereto; step 8, deposing and patterning a second metal layer on the interlayer insulation layer, and respectively forming a first source/drain in the drive TFT area and a second source/drain in the display TFT area, and the first source/drain contacts with the first polysilicon section though the first via, and the second source/drain contacts with the second polysilicon section though the second via.

2. The manufacture method of the Low Temperature Poly-silicon TFT substrate structure according to claim 1, wherein a thickness of the first polysilicon section is larger than a thickness of the second polysilicon section; a lattice dimension of the first polysilicon section is larger than a lattice dimension of the second polysilicon section; fractured crystals in the second polysilicon section are more than fractured crystals in the first polysilicon section.

3. The manufacture method of the Low Temperature Poly-silicon TFT substrate structure according to claim 1, wherein the substrate is a glass substrate, and material of the buffer layer is Silicon Oxide, Silicon Nitride or a combination of the two.

4. The manufacture method of the Low Temperature Poly-silicon TFT substrate structure according to claim 1, wherein material of the interlayer insulation layer is Silicon Oxide, Silicon Nitride or a combination of the two.

5. The manufacture method of the Low Temperature Poly-silicon TFT substrate structure according to claim 1, wherein a thickness difference between the amorphous silicon layer of the drive TFT area and the amorphous silicon layer of the display TFT area is larger than 500 A.

6. A Low Temperature Poly-silicon TFT substrate structure, comprising a drive TFT area and a display TFT area, and the drive TFT area comprises a substrate, a buffer layer on the substrate, a first polysilicon section on the buffer layer, a gate isolation layer on the buffer layer and the first polysilicon section, a first gate on the gate isolation layer and above the first polysilicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the first gate and a first source/drain on the interlayer insulation layer; the display TFT area comprises a substrate, a buffer layer on the substrate, a second polysilicon section on the buffer layer, a gate isolation layer on the buffer layer and the second polysilicon section, a second gate on the gate isolation layer and above the second polysilicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the second gate and a second source/drain on the interlayer insulation layer; wherein a thickness of the second polysilicon section is larger than a thickness of the first polysilicon section.

7. The Low Temperature Poly-silicon TFT substrate structure according to claim 6, wherein a lattice dimension of the first polysilicon section is larger than a lattice dimension of the second polysilicon section; fractured crystals in the second polysilicon section are more than fractured crystals in the first polysilicon section.

8. The Low Temperature Poly-silicon TFT substrate structure according to claim 6, wherein the substrate is a glass substrate, and material of the buffer layer is Silicon Nitride, Silicon Oxide, or a combination of the two; material of the interlayer insulation layer is Silicon Oxide, Silicon Nitride or a combination of the two.

9. The Low Temperature Poly-silicon TFT substrate structure according to claim 6, wherein a first via is formed in the interlayer insulation layer and the gate isolation layer in the drive TFT area and above the first polysilicon section and corresponding thereto, and the first source/drain contacts with the first polysilicon section though the first via; a second via is formed in the interlayer insulation layer and the gate isolation layer in the display TFT area and above the second polysilicon section and corresponding thereto, and the second source/drain contacts with the second polysilicon section though the second via.

10. The Low Temperature Poly-silicon TFT substrate structure according to claim 6, wherein a thickness difference between the first polysilicon section and the second polysilicon section is larger than 500 A.

11. A Low Temperature Poly-silicon TFT substrate structure, comprising a drive TFT area and a display TFT area, and the drive TFT area comprises a substrate, a buffer layer on the substrate, a first polysilicon section on the buffer layer, a gate isolation layer on the buffer layer and the first polysilicon section, a first gate on the gate isolation layer and above the first polysilicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the first gate and a first source/drain on the interlayer insulation layer; the display TFT area comprises a substrate, a buffer layer on the substrate, a second polysilicon section on the buffer layer, a gate isolation layer on the buffer layer and the second polysilicon section, a second gate on the gate isolation layer and above the second polysilicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the second gate and a second source/drain on the interlayer insulation layer; wherein a thickness of the second polysilicon section is larger than a thickness of the first polysilicon section; wherein a lattice dimension of the first polysilicon section is larger than a lattice dimension of the second polysilicon section; fractured crystals in the second polysilicon section are more than fractured crystals in the first polysilicon section; wherein the substrate is a glass substrate, and material of the buffer layer is Silicon Nitride, Silicon Oxide, or a combination of the two; material of the interlayer insulation layer is Silicon Oxide, Silicon Nitride or a combination of the two.

12. The Low Temperature Poly-silicon TFT substrate structure according to claim 11, wherein a first via is formed in the interlayer insulation layer and the gate isolation layer in the drive TFT area and above the first polysilicon section and corresponding thereto, and the first source/drain contacts with the first polysilicon section though the first via; a second via is formed in the interlayer insulation layer and the gate isolation layer in the display TFT area and above the second polysilicon section and corresponding thereto, and the second source/drain contacts with the second polysilicon section though the second via.

13. The Low Temperature Poly-silicon TFT substrate structure according to claim 11, wherein a thickness difference between the first polysilicon section and the second polysilicon section is larger than 500 A.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The technical solution and the beneficial effects of the present invention are best understood from the following detailed description with reference to the accompanying figures and embodiments.

[0043] In drawings,

[0044] FIG. 1 is a diagram of the step 1 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to prior art;

[0045] FIG. 2 is a diagram of the step 2 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to prior art;

[0046] FIG. 3 is a diagram of the step 3 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to prior art;

[0047] FIG. 4 is a diagram of the step 7 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to prior art;

[0048] FIG. 5 is a flowchart of a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0049] FIG. 6 is a diagram of the step 1 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0050] FIG. 7 is a diagram of the step 2 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0051] FIG. 8 is a diagram of the step 3 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0052] FIG. 9 is a diagram of the step 4 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0053] FIG. 10 is a diagram of the step 5 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0054] FIG. 11 is a diagram of the step 6 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0055] FIG. 12 is a diagram of the step 7 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention;

[0056] FIG. 13 is a diagram of the step 8 in a manufacture method of a Low Temperature Poly-silicon TFT substrate structure according to the present invention and also a sectional diagram of the Low Temperature Poly-silicon TFT substrate structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0057] For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments.

[0058] Please refer to FIG. 5. The present invention first provides a manufacture method of a Low Temperature Poly-silicon TFT substrate structure, comprising steps of:

[0059] step 1, as shown in FIG. 6, providing a substrate 1, and the substrate 1 comprises a drive TFT area and a display TFT area, and deposing a buffer layer 11 on the substrate 1.

[0060] specifically, the substrate 1 is a glass substrate, and material of the buffer layer 11 can be Silicon Oxide (SiOx), Silicon Nitride (SiNx) or a combination of the two.

[0061] step 2, as shown in FIG. 7, deposing an amorphous silicon layer 12 on the buffer layer 11, and patterning the polysilicon layer 12 so that a thickness of the amorphous silicon layer 12 in the display TFT area is larger than a thickness of the amorphous silicon layer 12 in the drive TFT area.

[0062] The polysilicon layer 12 is set to have different thicknesses corresponding to different areas, which can generate different crystallization results in the following Excimer Laser Annealing process.

[0063] Preferably, a thickness difference between the amorphous silicon layer 12 of the drive TFT area and the amorphous silicon layer 12 of the display TFT area is larger than 500 A.

[0064] step 3, as shown in FIG. 8, implementing an Excimer Laser Annealing process to the amorphous silicon layer 12 to make the amorphous silicon layer 12 to be crystallized and converted to be a polysilicon layer 13 after an Excimer Laser Annealing pretreatment.

[0065] step 4, as shown in FIG. 9, patterning the polysilicon layer 13 to obtain a first polysilicon section 14 in the drive TFT area and a second polysilicon section 15 in the display TFT area.

[0066] In the Excimer Laser Annealing process, because the thickness of the amorphous silicon layer 12 in the drive TFT area is smaller, and the thickness of the amorphous silicon layer 12 in the display TFT area is larger, different crystallization results are generated with the amorphous silicon layers 12 in the drive TFT area and the display TFT area under the function of the laser with the same energy. The polysilicon layer 13 with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer 13 in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current.

[0067] Therefore, in this embodiment, a thickness of the first polysilicon section 14 is larger than a thickness of the second polysilicon section 15. A lattice dimension of the first polysilicon section 14 is larger than a lattice dimension of the second polysilicon section 15; fractured crystals in the second polysilicon section 15 are more than fractured crystals in the first polysilicon section 14.

[0068] step 5, as shown in FIG. 10, deposing a gate isolation layer 16 on the first polysilicon section 14, the second polysilicon section 15 and the buffer layer 11.

[0069] step 6, as shown in FIG. 11, deposing and patterning a first metal layer on the gate isolation layer 16, and forming a first gate 17 and a second gate 18 respectively above the first polysilicon section 14 and the second polysilicon section 15 and corresponding thereto.

[0070] step 7, as shown in FIG. 12, deposing an interlayer insulation layer 19 on the gate isolation layer 16, the first gate 17 and the second gate 18, and forming a first via 20 and a second via 20 in the interlayer insulation layer 19 and the gate isolation layer 16 respectively above the first polysilicon section 14 and the second polysilicon section 15 and corresponding thereto.

[0071] The interlayer insulation layer 19 is deposed on the gate isolation layer 16, the first gate 17 and the second gate 18, and forming a first via 20 and a second via 20 in the interlayer insulation layer 19 and the gate isolation layer 16 respectively above the first polysilicon section 14 and the second polysilicon section 15 and corresponding thereto.

[0072] Specifically, material of the interlayer insulation layer 19 is Silicon Oxide, Silicon Nitride or a combination of the two.

[0073] step 8, as shown in FIG. 13, deposing and patterning a second metal layer on the interlayer insulation layer 19, and respectively forming a first source/drain 21 in the drive TFT area and a second source/drain 22 in the display TFT area, and the first source/drain 21 contacts with the first polysilicon section 14 though the first via 20, and the second source/drain 22 contacts with the second polysilicon section 15 though the second via 20.

[0074] In the aforesaid manufacture method of the Low Temperature Poly-silicon TFT substrate structure, by providing the amorphous silicon layers in the drive TFT area and the display TFT area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.

[0075] Please refer to FIG. 13. The present invention further provides a Low Temperature Poly-silicon TFT substrate structure, comprising a drive TFT area and a display TFT area, and the drive TFT area comprises a substrate 1, a buffer layer 11 on the substrate 1, a first polysilicon section 14 on the buffer layer 11, a gate isolation layer 16 on the buffer layer 11 and the first polysilicon section 14, a first gate 17 on the gate isolation layer 16 and above the first polysilicon section 14 and corresponding thereto, an interlayer insulation layer 19 on the gate isolation layer 16 and the first gate 17 and a first source/drain 21 on the interlayer insulation layer 19;

[0076] the display TFT area comprises a substrate 1, a buffer layer 11 on the substrate 1, a second polysilicon section 15 on the buffer layer 11, a gate isolation layer 16 on the buffer layer 11 and the second polysilicon section 15, a second gate 18 on the gate isolation layer 16 and above the second polysilicon section 15 and corresponding thereto, an interlayer insulation layer 19 on the gate isolation layer 16 and the second gate 18 and a second source/drain 22 on the interlayer insulation layer 19;

[0077] wherein a thickness of the second polysilicon section 15 is larger than a thickness of the first polysilicon section 14.

[0078] A lattice dimension of the first polysilicon section 14 is larger than a lattice dimension of the second polysilicon section 15; fractured crystals in the second polysilicon section 15 are more than fractured crystals in the first polysilicon section 14.

[0079] Specifically, a first via 20 is formed in the interlayer insulation layer 19 and the gate isolation layer 16 in the drive TFT area and above the first polysilicon section 14 and corresponding thereto, and the first source/drain 21 contacts with the first polysilicon section 14 though the first via 20.

[0080] A second via 20 is formed in the interlayer insulation layer 19 and the gate isolation layer 16 in the display TFT area and above the second polysilicon section 15 and corresponding thereto, and the second source/drain 22 contacts with the second polysilicon section 15 though the second via 20.

[0081] Specifically, the substrate 1 is a glass substrate, and material of the buffer layer 11 is Silicon Nitride, Silicon Oxide, or a combination of the two; material of the interlayer insulation layer 19 is Silicon Oxide, Silicon Nitride or a combination of the two.

[0082] Preferably, a thickness difference between the second polysilicon section 15 and the first polysilicon section 14 is larger than 500 A.

[0083] In the aforesaid Low Temperature Poly-silicon TFT substrate structure, the amorphous silicon layers in the drive TFT area and the display TFT area are set to have different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The uniformity of the grain boundary of the polysilicon layer in the display TFT area is better in the crystallization process. The uniformity of the current is better. The electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.

[0084] In conclusion, in the Low Temperature Poly-silicon TFT substrate structure and the manufacture method thereof according to the present invention, by providing the amorphous silicon layers in the drive TFT area and the display TFT area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.

[0085] Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.