A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

A junction field-effect transistor device includes an integrated temperature sensor, and a method of making the same is disclosed. A temperature sensor material having a first charge carrier polarity is implanted into an area of semiconductor material having a second charge carrier polarity, with the area being located adjacent to the junction field-effect transistor. The sensor material contains dopants and exhibits an electrical resistance that increases with a number of ionized ones of the dopants. The number of ionized dopants increases with the temperature of the material. First and second electrical terminals are provided spaced-apart on the sensor material for measuring the electrical resistance of the material. The measured electrical resistance may be translated into a temperature value for the junction field-effect transistor.

A new design of a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacturing the MOSFET are disclosed. The SiC MOSFET features a trench formed in SiC layers that includes a buried p-well region near the bottom of the trench that extends along a sidewall of the trench. The SiC MOSFET may also include a p-body and built-in channel on an opposite sides of the trench. The SiC MOSFET configurations may help prevent dielectric breakdown and bipolar degradation in the SiC.

Embodiments of the present disclosure illustrate a semiconductor device. The semiconductor device comprises a silicon carbide epitaxial layer, comprising: a p-type well region; a junction field effect region adjacent to the p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The semiconductor device further comprises an island-shaped oxide layer on the junction field effect region; a gate oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region and the island-shaped oxide; and a polycrystalline silicon layer on the gate oxide layer without contacting the island-shaped oxide.

A method includes providing a two-level gallium nitride (GaN) epitaxial substrate comprising a first GaN drift layer characterized by a first doping concentration and a second GaN drift layer disposed on the first GaN drift layer and characterized by a second doping concentration higher than the first doping concentration and forming a plurality of pedestals in the second GaN drift layer. Each of the plurality of pedestals is laterally separated by one of a plurality of funnels. The method also includes performing a channel regrowth process to regrow a plurality of n-type GaN channels, each disposed in one of the plurality of funnels, and performing a gate regrowth process to regrow p-type GaN. The method further includes patterning the p-type GaN to form a plurality of p-type GaN gates disposed in one of the plurality of n-type GaN channels, and forming source contacts, gate contacts, and a drain contact.