A semiconductor device includes an active region comprising a plurality of alternating trenches and mesas in an epitaxial layer, the plurality of alternating trenches and mesas extending in a first direction, and an edge termination region adjacent the active region and including a first edge termination region and a second edge termination region. The edge termination region includes first and second guard ring trenches adjacent the active region that are separated by a termination mesa that extends in the first direction in the first edge termination region and extends in a second direction, perpendicular to the first direction, in the second edge termination region. The termination mesa has a first width in the first edge termination region and the termination mesa has a second width in the second edge termination region that is different from the first width.

A semiconductor device includes a source electrode, a drain electrode and a gate. The gate controls a current flowing between the source electrode and the drain electrode. Capacitance between the gate and the drain electrode is first capacitance. Capacitance between the gate and the source electrode is second capacitance. A sum of the first capacitance and the second capacitance is equal to third capacitance. Total switching loss is a sum of first switching loss and second switching loss. The first switching loss is defined by a current variation rate, and the second switching loss is defined by a voltage variation rate. A capacitance ratio of the first capacitance to the third capacitance is set to a ratio to satisfying a relationship that the total switching loss is smaller than a predetermined value.

Power JFETs are provided that include a semiconductor layer structure that has an active region and a termination region, where the termination region at least partially surrounds the active region. These power JFETs further comprise a plurality of gate regions and a gate pad on the semiconductor layer structure, as well as a gate resistor that is electrically connected between the gate pad and the gate regions. The gate resistor extends around a periphery of the active region when the semiconductor device is viewed in plan view.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first source electrode, a second source electrode, and a drain electrode. The second nitride-based semiconductor layer includes a drift region doped, a first barrier region, and a second barrier region. The first and second barrier regions extend downward from a top surface of the second nitride-based semiconductor layer and are separated from each other by a portion of the drift region. The gate electrode is disposed on the first barrier region. The first source electrode is disposed on the portion of the drift region. The second source electrode is disposed on the second barrier region and is electrically coupled with the first source electrode. The drain electrode is connected to the first nitride-based semiconductor layer.

A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

A semiconductor device includes an active region comprising first and second mesa stripes and a trench between the mesa stripes. The trench has a first width between the first and second mesa stripes near a central portion of the first and second mesa stripes and a second width between the first and second mesa stripes near end portions of the first and second mesa stripes. The second width is less than the first width.

A power switch is disclosed. The power switch includes a metal-oxide semiconductor field-effect transistor (MOSFET) and a junction field effect transistor (JFET). The JFET is arranged in a cascode configuration with the MOSFET. The JFET includes a first plurality of JFET cells having a first gate resistance and a second plurality of JFET cells having a second gate resistance, wherein the second gate resistance is greater than the first gate resistance.

A junction field-effect transistor (JFET) is disclosed. The JFET includes a source contact coupled to a source region of the JFET and a gate contact coupled to a gate region of the JFET. The JFET further includes a first interlayer dielectric located above the source contact and the gate contact. In addition, the JFET includes a first layer of pad metal located on the first interlayer dielectric, wherein the first layer of pad metal is patterned to form a first gate-pad metal and a first source-pad metal. The JFET also includes a second interlayer dielectric located above the first layer of pad metal. In addition, the JFET includes a second layer of pad metal located on the second interlayer dielectric, wherein the second layer of pad metal is patterned to form a second gate-pad metal and a second source-pad metal.

A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of separated fins. Each of the separated fins has a length and a width measured laterally with respect to the length and includes a first fin tip disposed at a first end of the separated fin, a second fin tip disposed at a second end of the separated fin opposing the first end, a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity, and a source contact electrically coupled to the central region. The first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity. The FinFET further includes a first gate region surrounding the first fin tip and a second gate region surrounding the second fin tip.