One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region.

A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.