Disclosed are a vertical coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical coupling capacitance gate-controlled junction field effect transistor includes a base of a first doping type; two bottom gates of the second doping type, formed inside the base and spaced apart in the lateral direction; a top gate of the second doping type, formed inside the base, where the top gate is located above the interval between the two bottom gates, and an interval is formed between the top gate and the bottom gate; a dielectric layer, formed on the base and located on the top gate; and a coupling capacitance upper electrode, formed on the dielectric layer; where the top gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

A junction field-effect transistor (JFET) is disclosed. The JFET includes a source contact coupled to a source region of the JFET and a gate contact coupled to a gate region of the JFET. The JFET further includes a first interlayer dielectric located above the source contact and the gate contact. In addition, the JFET includes a first layer of pad metal located on the first interlayer dielectric, wherein the first layer of pad metal is patterned to form a first gate-pad metal and a first source-pad metal. The JFET also includes a second interlayer dielectric located above the first layer of pad metal. In addition, the JFET includes a second layer of pad metal located on the second interlayer dielectric, wherein the second layer of pad metal is patterned to form a second gate-pad metal and a second source-pad metal.

Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

A transistor that may include a drift layer formed on a substrate. A well implant layer formed within the drift layer wherein the well implant layer has a first gap. A gate implant layer formed within the drift layer and partially over the well implant layer wherein the gate implant layer has a second gap. A source implant layer formed within the drift layer and within the second gap of the gate implant layer. A plurality of gate contacts operatively connected to the gate implant layer. A source contact operatively connected to the source implant layer.

A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

A semiconductor device includes a semiconductor layer including a trench, wherein the trench is adjacent a mesa, a first metal silicide layer on a top portion of the mesa, and a second metal silicide layer on a bottom portion of the trench. The first metal silicide layer has a thickness that is no more than about 1 to 1.5 times greater than a thickness of the second metal silicide layer. Related methods of forming a semiconductor device are disclosed.

A junction field-effect transistor with asymmetric gates, and a method of making the same. A channel is constructed of semiconductor material, a source is located at a first end of the channel, and a drain is located at a second end. A first gate is located at and extends along a first side of the channel and creates a first depletion region, and a second gate is located at and extends along a second side of the channel and creates a second depletion region. The gates are physically asymmetric with regard to at least one of their relative position along the channel, their relative size, or their relative shape (e.g., one gate may project into the channel toward the other gate). The physical asymmetry of the first and second gates results in their respective depletion regions being asymmetric, which affects the ability to control electrical current flowing through the channel.

A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

A field-effect transistor with a shielded source, and a method of making the same. A volume of semiconductor material includes first and second vertically spaced ends and first and second laterally spaced sides. First and second laterally spaced gates are provided in the volume of semiconductor material. A source is located at the first end between the first and second gates, a drain is provided, and a channel extends therebetween. The first gate includes a lower first gate portion spaced below and extending beneath the source so as to create a turn in the channel around the lower first gate portion.