Disclosed is an array substrate including a base substrate and a gate metal layer, a semiconductor layer, a source-drain metal layer, and a pixel electrode layer that are formed on the base substrate. The gate metal layer includes gate lines, gate electrodes of thin film transistors, and a plurality of first sensing lines extending along a row direction. The semiconductor layer includes an active layer of the thin film transistors, and a plurality of first photosensitive elements and a plurality of second photosensitive elements that are insulated from each other. The source-drain metal layer includes data lines, source electrodes and drain electrodes of the thin film transistors, and a plurality of second sensing lines extending along a column direction. Also disclosed are a method of fabricating the array substrate, an optical touch screen and a display device.

A photodiode includes a cap layer defining an inboard side and an outboard side. A plurality of pixels are formed in the cap layer extending from the inboard side to the outboard side. At least a portion of the cap layer is defined in between the pixels. A metal barrier is in between the pixels and is operatively connected to the inboard side of the cap layer in between the pixels to reflect light rays into the cap layer reducing the leakage of photons between the pixels.

In a photoelectric changing unit, a photoelectric conversion unit converts light into electric charge, and an electric charge accumulation unit accumulates the electric charge in a polygonal area whose plurality of sides are adjacent to the photoelectric conversion unit on a light receiving surface. A voltage generation unit accumulates the electric charge and generates a voltage according to an amount of the accumulated electric charge. A first transfer unit transfers the electric charge from the photoelectric conversion unit to the electric charge accumulation unit when an instruction on a transfer to the electric charge accumulation unit is issued. A second transfer unit transfers the electric charge from the electric charge accumulation unit to the voltage generation unit when an instruction on a transfer to the voltage generation unit is issued.

The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.

An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.

According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as holes, effectively increase the absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. Their thickness dimensions allow them to be conveniently integrated on the same Si chip with CMOS, BiCMOS, and other electronics, with resulting packaging benefits and reduced capacitance and thus higher speeds.

A method produces a light-receiving device by growing a light-receiving layer having an undoped multi-quantum well structure; growing a cap layer on the light-receiving layer while the cap layer is doped with a p-type impurity during its growth; growing a mesa structure; growing a protective film on surfaces of the mesa structure; and annealing to form a p-n junction. The mesa structure is defined by a surrounding trench. Alternatively, a selective growth mask can be formed on the light-receiving layer whereafter the cap layer is grown on the light-receiving layer by use of the mask. In the alternative, the p-n junction is formed by diffusing p-type impurity from a p-type contact layer of the cap layer through a concentration adjusting layer thereof to the light-receiving layer.

A semiconductor detector device comprises a layer of semiconductor material for generating charge in response to an input event and an array of pixels for collecting charge. Tracks are connected to the pixels to supply signals representing the collected charge to a reader circuit. The pixels are grouped into sets, all the pixels within a set being connected to the same track, the sets of pixels being interwoven so that so that any group of n adjacent pixels capable of collecting charge generated by a single input event is connected to a combination of n tracks that is unique to the group of pixels, where n has a value of one of 2, 3 or 4. This allows detection of position of the area of charge collection on the basis of temporally coincident signals on a combination of at least n tracks.

A method of manufacturing a semiconductor device includes forming at least one sacrificial layer on a substrate during a complementary metal-oxide-semiconductor (CMOS) process. An absorber layer is deposited on top of the at least one sacrificial layer. A portion of the at least one sacrificial layer beneath the absorber layer is removed to form a gap over which a portion of the absorber layer is suspended. The sacrificial layer can be an oxide of the CMOS process with the oxide being removed to form the gap using a selective hydrofluoric acid vapor dry etch release process. The sacrificial layer can also be a polymer layer with the polymer layer being removed to form the gap using an O.sub.2 plasma etching process.