A quantum computing apparatus, including a quantum circuit device; and an interposer including a connectorization layer including a plurality of terminals for connecting the quantum computing apparatus to a corresponding plurality of cables and a plurality of signal lines electrically coupled, via electrical contacts, to the plurality of terminals; and at least one intermediate layer between the quantum circuit device and the connectorization layer, the at least one intermediate layer comprising an integrated circuit layer, the at least one intermediate layer being electrically coupled to the signal lines of the interposer. The interposer is configured to supply the quantum circuit device, during operation of the quantum computing apparatus, at least control signals and readout signals to and from the plurality of cables.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.

A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.

An approach is provided for adiabatic quantum annealing (computing, AQC). There is disclosed an apparatus comprising a first quantum dot and a second quantum dot forming a first kind of double quantum dot; and a third quantum dot and a fourth quantum dot forming a second kind of double quantum dot. The apparatus also comprises a first control element for adjusting a capacitance of a capacitive element; a second control element for supplying a control voltage to the first kind of double quantum dot; a metallic or superconducting contact to capacitively couple the first kind of double quantum dot to the fourth quantum dot; and an electric charge sensor for providing an indication of the state of the first kind of double quantum dot. The present invention also relates to a method for controlling the apparatus.

Aspects of the present disclosure generally pertain to a magnetic field sensor with flex coupling structures. Aspects of the present disclosure are more specifically directed toward Nanoscale Superconducting Quantum Interference Devices (nanoSQUIDs) with very low white flux noise characteristics can be fashioned into very sensitive magnetic field sensors by using external structures to increase the amount of flux that passes through the nanoSQUID aperture. One such structure is a superconducting coupling loop that shares part of a circuit with the nanoSQUID, and couples flux into the nanoSQUID primarily through kinetic inductance rather than geometric inductance.

A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

A phase quantum bit is disclosed. In one embodiment, the phase quantum bit may comprise a Josephson junction and a distributed element coupled to the Josephson junction. The distributed element provides a capacitive component and an inductive component of the phase quantum bit.