A combined semiconductor controlled circuit (CSCC) includes a semiconductor controlled switch (SCS). The SCS includes anode, cathode, anode gate and cathode gate terminals connected to P.sub.1 anode, N.sub.2 cathode, N.sub.1 anode gate and P.sub.2 cathode gate layers. The SCS also includes P-N junctions between P.sub.1 anode and N.sub.1 anode gate layers, N.sub.1 anode gate and P.sub.2 cathode gate layers and P.sub.2 cathode gate and N.sub.2 cathode layers. The CSCC also includes a Zener diode having a current path flowing from the cathode terminal to the anode gate terminal, a feedback resistor connecting cathode and cathode gate terminals and a substrate. A solid-state spark chamber includes a CSCC, a DC bias voltage source and an RC load having a parallel-connected load resistor and capacitor. The solid-state spark chamber also includes a plurality of measurement terminals and a ground. A method of making a solid-state spark chamber includes connecting the above components.

In a vertical switch having various doped layers, such as npnp or npn layers, and an array of trenched gates, a p-body layer is formed over an n-drift layer. A portion of the p-body layer is inverted by the voltage on the gate to form an n-channel to turn the device on. In a conventional device, the p-body layer is formed by implantation of p-dopants into the n-layer and then diffused. Since the p-body is fairly thick, diffusion takes a long time, resulting in the various layers having poor definition and imprecise characteristics. The device is improved by forming the p-body by epitaxial growth and varying the p-dopant concentration in the p-body to achieve the desired device characteristics. The top portion of the p-body may be enhanced by an implantation of additional p-dopants to achieve a desired turn-on voltage but not affecting the breakdown voltage of the device.

The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

Electronic components, more particularly triacs, are provided. An example triac is formed inside and on top of a semiconductor substrate. The triac comprising: on the side of a first surface of the substrate, a first doped region of a first conductivity type and connected to a first conduction terminal; on the side of a second surface of the substrate opposite to the first surface, a second doped region of the first conductivity type and connected to a second conduction terminal; and a gate region connected to a control terminal. The first and second regions respectively have first and second parallel lateral surfaces. Between the first and second parallel lateral surfaces is a separation region not covered by the first and second regions, the separation region shaped as a strip extending along a first direction inside of the gate region and exhibiting an inflection outside of the gate region.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.