A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.

A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate

A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.

A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.