A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.

A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.

A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed.

A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.

A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.