A method for manufacturing a silicon carbide semiconductor device according to the technology disclosed in the present specification includes: forming a drift layer on an upper surface of a silicon carbide semiconductor substrate; forming a hard mask on the upper surface of the drift layer by anisotropic etching; and forming a first ion-implanted region in a surface layer of the drift layer by implanting ions into the drift layer in a state in which the hard mask is formed, in which the hard mask includes a sidewall perpendicular to the upper surface of the drift layer.

To manufacture a MOSFET device, first, a patterned mask is utilized to implant first ions, to form a well region in which diffusion is not easy. Then, the patterned mask and spacers on its sidewalls are utilized to implant second ions in self-alignment with a source region. Further, the characteristic that the second ions are easier to diffuse than the first ions is utilized to form a semi-superjunction located at a bottom of the well region and connected to the bottom of the well region. The semi-superjunction effectively expands a junction depth of the well region, so that a withstand voltage of the device is increased to achieve high-conduction performance of the device, and also shifts a peak of electric field strength below a gate oxide layer to below the well region, so that the electric field strength below the gate oxide layer is effectively reduced and is more uniform.

The present application discloses an SiC MOSFET device, including an SiC epitaxial layer in which a trench gate is formed, wherein a first bottom doped region is formed below a bottom surface of a gate trench, a second deep doped region with spacing from the gate trench is formed in the SiC epitaxial layer, the first bottom doped region is connected to a source so that voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by gate-source voltage; the second deep doped region extends downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region is located below a bottom surface of the first bottom doped region; a top of the second deep doped region is connected to the source. The present application further discloses a method for manufacturing an SiC MOSFET device.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 110.sup.15/cm.sup.3.

A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.

A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

Provided are a silicon carbide semiconductor device that is capable of preventing breakdown voltage degradation in the edge termination structure and a method of manufacturing the same.

The p-type regions 31, 32 and the p-type region 33, which serves as an electric field relaxation region and is connected to the first p-type base regions 10, are positioned under the step-like portion 40, and the bottom surfaces of the p-type regions 31, 32, 33 are substantially flatly connected to the bottom surface of the first p-type base regions 10.

The first base regions have an impurity concentration of 410.sup.17 cm.sup.3 or higher. The p-type region 33 is designed to have a lower impurity concentration than the first base regions 10 and higher than the p-type regions 31, 32. In this way, the breakdown voltage degradation in the edge termination structure 102 can be prevented.