A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

A method can include receiving a first power supply voltage at a first terminal at a first side of an IC device and providing a row of stacked pairs of insulated gate field effect transistor (IGFETs) substantially at the second side of the IC device. Each stacked pair can include a first and second IGFET of different conductivity types. Each IGFET can include multiple channels and a control gate that substantially surrounds the channels. A first power supply can be coupled from the first power supply terminal to a first source of one IGFET of the stacked pair via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side below the row of stacked pairs. Corresponding devices and systems are also disclosed.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10 relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.

An upper electrode is separated from a lower electrode inside a trench by an intermediate insulating film. A first resistor is connected between the upper electrode and the input terminal. A second resistor is connected between the lower electrode and the input terminal. Gate-emitter capacitance of the lower electrode is smaller than gate-emitter capacitance of the upper electrode.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Provided is a semiconductor device including: a current detection portion through which a detection current corresponding to a main current of a transistor portion flows; a current detection pad which is arranged above a semiconductor substrate and arranged side by side with the current detection portion in a first direction; a built-in resistance portion which is provided above the semiconductor substrate and connects the current detection portion and the current detection pad; and a gate wiring which is arranged above the semiconductor substrate and is connected to the gate conductive portion, in which the built-in resistance portion and the gate wiring are arranged side by side in the first direction between the current detection portion and the current detection pad.

Some examples include a resistor structure formed from interconnect line segments in multiple metalization layers of an integrated circuit device. The line segments include contacts from at least one dummy transistor.

The present disclosure provides a method of fabricating radio frequency (RF) circuits using three-dimensional (3D), hybrid wafer-level bonded wafers. In one aspect, a first, bottom silicon-on-insulator (SOI) wafer and a second, top SOI wafer are provided. Complementary metal-oxide semiconductor processing is then performed on both the first and second SOI wafers to fabricate transistors and form RF circuits on each wafer. The second wafer is then bonded to the first wafer to electrically couple the RF circuits together. In an aspect, the 3D fabrication method enables RF circuits that are designed using transistor structures stacked in a three-dimensional (3D) folded configuration using a plurality of wafers. In one aspect, the RF circuit uses mirrored portions that are folded together during the wafer bonding process. In another aspect, the RF circuit uses asymmetric portions between the top versus bottom wafers.