A microelectronic structure that includes a nanosheet transistor that includes a first source/drain and a second source/drain. A trench epi extending from a backside surface of the first source/drain. A backside contact that wraps around the trench epi and is in contact with a backside surface of the first source/drain.

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

A ferroelectric field effect transistor includes a channel layer, a gate electrode facing the channel layer, a ferroelectric layer between the channel layer and the gate electrode, and a channel intermediate layer between the channel layer and the ferroelectric layer, wherein the channel layer and the channel intermediate layer each include an oxide semiconductor material, and a concentration of oxygen vacancies in the channel intermediate layer may be greater than a concentration of oxygen vacancies in the channel layer.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a logic cell on a substrate, and a first metal layer on the logic cell. The first metal layer includes first and second power lines and first to third lower lines on first to third wiring tracks therebetween. The first to third wiring tracks extend in parallel in the first direction. The first lower line includes first and second lines spaced apart in the first direction from each other at a first distance. The third lower line includes third and fourth lines spaced apart in the first direction at a second distance. The first line has a first end facing the second line. The third line has a second end facing the fourth line. A curvature at the first end is substantially the same as that at the second end.

A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.

A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in. ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.