An electronic device includes: a first substrate having a first surface and a second surface opposite from the first surface; a second substrate facing the first surface; driven elements provided at the second substrate; a drive circuit facing the second surface; a first interconnect provided at the first surface; a second interconnect provided at the second surface; a through-substrate interconnection part penetrating the first substrate in a thickness direction thereof; a first bump part; and a second bump part. The drive circuit is capable of outputting drive signals for driving the driven elements. The through-substrate interconnection part electrically connects the first interconnect and the second interconnect. The first bump part electrically connects the first interconnect and the driven elements. The second bump part electrically connects the second interconnect and the drive circuit. The through-substrate interconnection part has an electrical resistance lower than an electrical resistance of the second bump part.

Provided is a display substrate, which includes a base substrate, a circuit structure layer disposed on the base substrate, multiple ultrasonic sensing elements and multiple micro light-emitting elements. The multiple ultrasonic sensing elements are disposed on a side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer, and the multiple light-emitting elements are disposed on the side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer. An orthographic projection of the multiple ultrasonic sensing elements on the base substrate does not overlap with an orthographic projection of the multiple micro light-emitting elements on the base substrate.

A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

An optoelectronic component and a method for the producing an optoelectronic component are disclosed. In an embodiment, the component comprises an active zone for generating electromagnetic radiation, wherein the active zone adjoins at least one layer arrangement of a semiconductor material, wherein the layer arrangement comprises at least two layers, wherein the two layers are formed in such a way that at an interface between the two layers a piezoelectric field is provided, the piezoelectric field configured to provide an electrical voltage drop at the interface, wherein a peak doping region is provided at the interface of the two layers in order to reduce the electrical voltage drop, wherein, in the direction away from the active zone, a doping of the peak doping region increases at least by a first percentage value and then decreases by at least a second percentage value, and wherein the first percentage value and the second percentage value are greater than 10% of a maximum doping of the peak doping region.

In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.

The present invention features methods of treating patients with chronic heart failure by administering a neuregulin polypeptide within a dosage range which is both effective and safe.

A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing methods are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a piezoelectric film that is located between the first and the second cavities and continuously separates these two cavities. The plan views of the first and the second cavities have an overlapped region, which is a polygon that does not have any parallel sides. The piezoelectric film in this inventive concept is a continuous film without any through-hole in it, therefore it can offer improved acoustic resonance performance.

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing method are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a piezoelectric film that is located between the first and second cavities and continuously separates these two cavities. The plan views of the first and the second cavities have an overlapped region, which is a polygon that does not have any parallel sides. The piezoelectric film of this inventive concept is a continuous film without any through-hole in it, therefore it can offer improved acoustic resonance performance.