A vertical junction field effect transistor includes a trench structure laterally arranged between mesa regions along a first lateral direction. The trench structure extends into a semiconductor body from a first surface of the semiconductor body. Each of the mesa regions includes a mesa channel region of a first conductivity type. The vertical junction field effect transistor further includes a gate region of a second conductivity type. The gate region adjoins at least part of opposite sidewalls of the trench structure and to a bottom side of the trench structure. The trench structure includes a silicon layer adjoining the gate region at the bottom side of the trench structure. A first thickness of the gate region at the bottom side of the trench structure is larger than a second thickness of the gate region at each of the opposite sidewalls of the trench structure.

A method includes forming a semiconductor device that includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.