A film comprising a polymer compound and a low molecular weight compound having carrier transportability, wherein the content of the low molecular weight compound is 5 to 40 parts by mass with respect to 100 parts by mass of the sum of the polymer compound and the low molecular weight compound, the diffraction intensity A specified by the following measuring method A is 3 to 50, and the intensity ratio (A/B) of the diffraction intensity A specified by the following measuring method A to the diffraction intensity B specified by the following measuring method B is 30 or less: (Measuring method A) the diffraction intensity A is the maximum diffraction intensity in a range of scattering vector of 1 nm.sup.1 to 5 nm.sup.1 in a profile obtained by an Out-of plane measuring method using a film X-ray diffraction method; (Measuring method B) the diffraction intensity B is the maximum diffraction intensity in a range of scattering vector of 10 nm.sup.1 to 21 nm.sup.1 in a profile obtained by an In-plane measuring method using a film X-ray diffraction method.

In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

A film comprising a polymer compound and a low molecular weight compound having carrier transportability, wherein the content of the low molecular weight compound is 5 to 40 parts by mass with respect to 100 parts by mass of the sum of the polymer compound and the low molecular weight compound, the diffraction intensity A specified by the following measuring method A is 3 to 50, and the intensity ratio (A/B) of the diffraction intensity A specified by the following measuring method A to the diffraction intensity B specified by the following measuring method B is 30 or less: (Measuring method A) the diffraction intensity A is the maximum diffraction intensity in a range of scattering vector of 1 nm.sup.1 to 5 nm.sup.1 in a profile obtained by an Out-of plane measuring method using a film X-ray diffraction method; (Measuring method B) the diffraction intensity B is the maximum diffraction intensity in a range of scattering vector of 10 nm.sup.1 to 21 nm.sup.1 in a profile obtained by an In-plane measuring method using a film X-ray diffraction method.

Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

A semiconductor die includes: a silicon-on-insulator (SOI) substrate having a silicon device layer, a bulk silicon substrate, and a buried oxide layer separating the silicon device layer from the bulk silicon substrate; a lateral power MOSFET (metal-oxide-semiconductor field-effect transistor) in a first device region of the silicon device layer; and an additional semiconductor device in a second device region of the silicon device layer and having a lower breakdown voltage than the lateral power MOSFET. The silicon device layer has a first thickness in a first part of the first device region and a second thickness in a second part of the first device region, the second thickness being greater than the first thickness. The silicon device layer has the first thickness throughout the second device region. Additional semiconductor die embodiments are also described.

A semiconductor die includes: a silicon-on-insulator (SOI) substrate having a silicon device layer, a bulk silicon substrate, and a buried oxide layer separating the silicon device layer from the bulk silicon substrate; a lateral power MOSFET (metal-oxide-semiconductor field-effect transistor) in a first device region of the silicon device layer; and an additional semiconductor device in a second device region of the silicon device layer and having a lower breakdown voltage than the lateral power MOSFET. The silicon device layer has a first thickness in a first part of the first device region and a second thickness in a second part of the first device region, the second thickness being greater than the first thickness. The silicon device layer has the first thickness throughout the second device region. Additional semiconductor die embodiments are also described.

A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.