A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. ALEFT-ISD-LTSEE is a device that reduces the cost of manufacture while allowing scaling and improving device performance. One of the requirements of IoT devices is the ability to store data on chips designed. This requires integratable memory with the low cost of manufacture. NVM-ALEFT-ISD-LTSEE is an easily integratable non-volatile memory device that is integratable with the ALEFT-ISD-LTSEE devices with minimum additional processing. ALEFT-ISD-LTSEE with NVM-ALEFT-ISD-LTSEE is hence a suitable technology combination for the IoT devices.

A non-volatile memory device includes a substrate, a source line in the substrate, a semiconductor epitaxial layer on the substrate, a device isolation structure, a trench, a floating gate, a control gate, a tunnel oxide layer, an inter-gate dielectric layer, a drain region, and a bit line. The device isolation structure is disposed in the semiconductor epitaxial layer and extends in a first direction. The trench is formed in the semiconductor epitaxial layer and crosses the device isolation structure in a second direction. The floating gate, the control gate, the tunnel oxide layer, and the inter-gate dielectric layer are in the trench, and the control gate extends in the second direction. The drain region is formed in the semiconductor epitaxial layer on both sides of the control gate. The bit line extends on the semiconductor epitaxial layer in the first direction and is electrically connected to the drain region.

A semiconductor structure is provided. The semiconductor structure includes a pad layer, a first conductive layer, a second conductive layer, an interlayer dielectric layer, and a control gate. The pad layer is disposed on a substrate. The first conductive layer is disposed on the pad layer. The second conductive layer is disposed on the first conductive layer. The interlayer dielectric layer is disposed on the first conductive layer and the second conductive layer and is in contact with top surfaces of the first conductive layer and the second conductive layer. The control gate is disposed on the interlayer dielectric layer.

A semiconductor device and a method for manufacturing the same, and a NAND memory device are disclosed. The method comprises: forming a substrate that comprises a first active region and an isolation region; forming a first groove between the isolation region and the first channel region, the first groove being partially located in the isolation region, and not penetrating through the isolation region; forming a first gate insulating layer covering the first groove and the first channel region; forming a first gate on the first gate insulating layer, the first gate covering the first channel region and filling the first groove.

A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.

A shield gate trench MOSFET device includes a substrate and a trench in the substrate. A lower portion of the trench is filled with a shield gate dielectric layer and a first polysilicon layer. An upper portion of the trench is filled with a first dielectric layer, a second polysilicon layer, and a second dielectric layer. The second dielectric layer is located above the second polysilicon layer, and the top of the second polysilicon layer is lower than the surface of the substrate. A well region is located outside the trench, and a Schottky implantation region is located outside the well region. The bottom of the Schottky implantation region is higher than the bottom of the well region. The well region includes a source region and a well contact region. The well contact region is located between the source region and the Schottky implantation region.

A semiconductor structure includes a substrate, a dielectric structure, a floating gate, and a control gate. The substrate has a protrusion, a first recess, and a second recess, wherein the first recess and the second recess are on opposite sides of the protrusion. The dielectric structure extends from the first recess and the second recess to above a top surface of the protrusion. The floating gate is disposed over the substrate and adjoins a sidewall of the dielectric structure. The control gate is disposed over the floating gate and extends over a top surface of the dielectric structure to directly above the protrusion.

Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.

The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.