A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel insulating film, forming an integral insulating film on the floating gate, and forming a control gate on the integral insulating film. The floating gate is formed on the tunnel insulating film by forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity later containing adsorbed boron or germanium on the seed layer, and forming a cap layer containing silicon on the impurity layer.

A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.

Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.

A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. A charge storage layer is formed over the capacitor region and the memory region including over the select gate and the plurality of lines. A control gate layer is formed over the charge storage layer over the capacitor region and over the memory region. The control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of a capacitor over the capacitor region. The plurality of lines are connected to the capacitor region to form a second electrode of the capacitor.

A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.