A semiconductor device includes a substrate, a source electrode extending, a drain electrode, a first gate electrode extending in a first direction and provided between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on the substrate in the first direction of the first gate electrode between the source electrode and the drain electrode, a gate pad provided so as to interpose the first gate electrode between the second gate electrode and the gate pad and electrically connected to the first gate electrode, a gate wiring provided above the source electrode and electrically connecting the gate pad and the second gate electrode, and a guard metal layer provided between the gate wiring and the drain electrode, at least a part of the guard metal layer being provided above the source electrode and electrically connected to the source electrode.

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

A gallium nitride-based semiconductor device includes an amorphous glass substrate having a first surface and a second surface opposite to the first surface; a gallium nitride-based semiconductor layer on the first surface of the amorphous glass substrate, and a compensation layer on the second surface of the amorphous glass substrate. A thermal expansion coefficient of the compensation layer is more than a thermal expansion coefficient of the amorphous glass substrate and less than a thermal expansion coefficient of the gallium nitride-based semiconductor layer.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

A method comprises forming a first gate of a first field effect transistor (FET) device over a first channel region of a first fin arranged on a substrate, forming a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, etching to remove portions of the insulator material and define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.

A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

A semiconductor device according to embodiments of the present invention is a field-effect transistor including a gate electrode between a source electrode and a drain electrode, wherein carriers travel between the source electrode and the drain electrode, a channel control layer is provided between a channel through with the carriers travel and the gate electrode, a recess is disposed at least in part of a surface in contact with the gate electrode on a source electrode side in the channel control layer, and a part of the gate electrode is filled in the recess.

A high electron mobility transistor includes: a channel layer through which carriers are to flow; a pair of respective main electrodes coupled to one end and another end of the channel layer; a barrier layer that is disposed at the channel layer and induces the carriers; a gate electrode disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween; a first spacer layer that is disposed between the channel layer and the barrier layer and decreases alloy scattering; and a second spacer layer that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode and traps the carriers.