Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Techniques are provided herein to form semiconductor devices within a standard unit cell having topside metal tracks that are offset from backside metal tracks. Stacked transistors are provided such that a source or drain region of one device is located vertically over the source or drain region of the other device. Both frontside and backside contacts may be formed to contact either top or bottom surfaces of the corresponding source or drain regions. Topside metal tracks are used to provide signal and power to various transistor elements of the top semiconductor device while backside metal tracks are used to provide signal and power to various transistor elements of the bottom semiconductor device. The topside tracks are offset from the backside tracks such that one topside track is aligned along one boundary of a standard unit cell and one backside track is aligned along the opposite standard unit cell boundary.

Provided is a semiconductor device including: a channel structure; a gate structure on the channel structure; a backside isolation structure on the gate structure; an alignment spacer layer on a lower side surface of the backside isolation structure, the alignment spacer layer comprising a material different from the backside isolation structure; a source/drain pattern on the channel structure; and a backside contact structure on the source/drain pattern.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

A semiconductor device includes a support substrate; a bonding layer on the support substrate; a first frontside wiring structure on the bonding layer; a second frontside wiring structure on the bonding layer, wherein the second frontside wiring structure is spaced apart from the first frontside wiring structure in a first direction; a frontside wiring pattern on the first frontside wiring structure and the second frontside wiring structure, wherein the frontside wiring pattern extends in the first direction; a frontside source/drain contact on the frontside wiring pattern; a source/drain pattern on the frontside source/drain contact; a backside wiring pattern on the source/drain pattern; a backside wiring structure on the backside wiring pattern; and a first via extending into the bonding layer, wherein the first via is in contact with the second frontside wiring structure, wherein the first via overlaps the second frontside wiring structure in a second direction.

Backside and frontside contact structures wrapping around source/drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source/drain regions provides source/drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source/drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A semiconductor device including a base insulation layer, a channel structure positioned on a first surface of the base insulation layer, a gate structure surrounding the channel structure, and a first source/drain pattern and a second source/drain pattern arranged spaced apart from each other along a first direction on both sides of the channel structure. The first and second source/drain patterns includes a liner layer and a filling layer on an inner surface of the liner layer, a portion of the lower and the side surfaces of the first source/drain pattern are covered by the base insulation layer. The liner layer includes a carbon-doped silicon germanium.

A method includes forming a base substrate having a semiconductor substrate having a first dopant concentration, a bottom epitaxial semiconductor layer having a second dopant concentration greater than the first dopant concentration, and a top epitaxial semiconductor layer having a third dopant concentration less than the second dopant concentration, forming a front-end-of-line (FEOL) structure on the top epitaxial semiconductor layer, forming a first back-end-of-line (BEOL) structure on the FEOL structure, removing the semiconductor substrate to expose the bottom epitaxial semiconductor layer, and forming a second BEOL structure to be apart from the first BEOL structure with the FEOL structure therebetween by removing the bottom epitaxial semiconductor layer by wet etching to expose the top epitaxial semiconductor layer and patterning the top epitaxial semiconductor layer.

A source/drain region is formed for a nanostructure transistor of a semiconductor device such that a hollow cavity extends into the source/drain region from a top of the source/drain region into the source/drain region. In some implementations, the cavity extends fully through the depth of the source/drain region. The cavity results from partial epitaxial growth of one or more epitaxial layers of the source/drain region. A metal core of the source/drain region is formed in the cavity and electrically coupled to a source/drain contact of a nanostructure transistor such that electrically conductive material is recessed within the source/drain region. This provides a greater amount of surface area for the source/drain contact to contact the source/drain region than if the source/drain region were fully filled in with epitaxially-grown semiconductor material.