A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a vertical metal gate disposed between a first and second source/drain (S/D) epitaxial (EPI) structure and having a set of vertically-stacked, horizontal channels, all but the top channel connecting the first and second S/D EPI structures through the vertical metal gate. A high-K dielectric material is disposed between the vertical metal gate and each of the horizontal channels, and vertical spacer layers separate the vertical metal gate from the S/D EPI structures. A low-K dielectric structure is disposed above the top-most portion of the vertical metal gate and fills a recess above the vertical metal gate and between the first vertical spacer layer and the second vertical spacer layer.

A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.

Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.

An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.

Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

A semiconductor device includes two source/drain features, a gate structure, a first contact plug, a second contact plug, a conductive line, and a nitride capping layer. The two source/drain features are laterally arranged to each other. The one or more channel layers connects the two source/drain features. The gate structure engages the one or more channel layers and interposes the two source/drain features. The first contact plug extends from above a first source/drain feature of the two source/drain features to the first source/drain feature. The second contact plug extends from below a second source/drain feature of the two source/drain features to the second source/drain feature. The conductive line is disposed underneath the second contact plug and electrically coupled to the second contact plug. The nitride capping layer is disposed between the second contact plug and the conductive line.