According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

A semiconductor device, including: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cut including a first portion penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner sidewalls of the plurality of nanosheets in the first horizontal direction; a first source/drain region on a first side of the active cut on the insulating pattern, wherein the first source/drain region is on first outer sidewalls of the plurality of nanosheets; a second source/drain region on a second side of the active cut opposite to the first side of the active cut in the first horizontal direction on the insulating pattern, wherein the second source/drain region is on second outer sidewalls of the plurality of nanosheets; and a bottom source/drain contact penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source/drain contact is electrically connected to the second source/drain region, and wherein the bottom source/drain contact overlaps the first portion of the active cut in the first horizontal direction, wherein a width of the upper surface of the first portion of the active cut in the first horizontal direction is smaller than a width of a lower surface of the first portion of the active cut in the first horizontal direction.

A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.

A method includes forming a first transistor comprising a first channel region, a first gate structure surrounding the first channel region, and first source/drain regions on opposite sides of the first gate structure; forming a second transistor comprising a second channel region, a second gate structure surrounding the second channel region, and second source/drain regions on opposite sides of the second gate structure; forming a front-side contact on a top end of a first one of the first source/drain regions of the first transistor; forming a first back-side contact extending from a bottom end of the first one of the first source/drain regions of the first transistor to a bottom end of a first one of the second source/drain regions of the second transistor.

Embodiments are disclosed for a method for fabricating a semiconductor device. The method includes forming a recess under a region for a source/drain (S/D). The method further includes depositing a sacrificial placeholder liner conformally. Additionally, the method includes performing a sacrificial material overfill. Further, the method includes performing an etch back of the sacrificial material overfill. Also, the method includes performing S/D epitaxial (epi) growth over a remaining placeholder sacrificial liner to generate an S/D epi for the S/D.

Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

A method for forming an integrated circuit device, the method comprising: forming a stack of field effect transistors, FETs, comprising a bottom FET and a top FET; forming a first trench underneath the bottom FET; forming a first hole, between the first trench and a first source/drain region of the bottom FET; forming a second hole, between the first hole and a contact of a contact layer arranged above the top FET; performing a first metal deposition to fill the first hole; the second hole; and part of the first trench, with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer below the recessed metal; performing a second metal deposition to fill the first trench with metal, thereby forming a first backside wiring line in the first trench.

Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.