A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.

A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Provided is a semiconductor device including: a substrate; an active pattern on an upper side of the substrate; a gate structure on and intersecting the active pattern; a source/drain pattern on a side face of the gate structure and connected to the active pattern; an etch stop layer extending along an upper side of the substrate and an outer face of the source/drain pattern; a back side source/drain contact in the substrate, the back side source/drain contact being connected to the source/drain pattern; and a back side wiring structure on a lower side of the substrate and connected to the back side source/drain contact, wherein the back side source/drain contact extends along a part of a side face of the source/drain pattern, and wherein a part of the back side source/drain contact farthest from the lower side of the substrate is in contact with the etch stop layer.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain region, a second source/drain region adjacent the first source/drain region, an interlayer dielectric layer disposed between the first source/drain region and the second source/drain region, and a conductive feature disposed in the interlayer dielectric layer between the first source/drain region and the second source/drain region. The conductive feature includes a first portion and a second portion extending from the first portion, and an angle is formed between the first portion and the second portion. The angle is less than about 180 degrees. The conductive feature is electrically connected to the first source/drain region.

Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

A three-dimensional semiconductor device may include a first active region, which includes a first channel pattern and a first source/drain pattern connected to each other, on a substrate, a second active region, which includes a second channel pattern and a second source/drain pattern connected to each other, on the first active region, a gate electrode on the first and second channel patterns, a bottom active contact electrically connected to the first source/drain pattern and extended from the first source/drain pattern in a first direction, a lower metal layer provided below the bottom active contact, the lower metal layer including bottom via patterns and bottom interconnection lines electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the same.

A semiconductor device includes two source/drain features, a gate structure, a first contact plug, a second contact plug, a conductive line, and a nitride capping layer. The two source/drain features are laterally arranged to each other. The one or more channel layers connects the two source/drain features. The gate structure engages the one or more channel layers and interposes the two source/drain features. The first contact plug extends from above a first source/drain feature of the two source/drain features to the first source/drain feature. The second contact plug extends from below a second source/drain feature of the two source/drain features to the second source/drain feature. The conductive line is disposed underneath the second contact plug and electrically coupled to the second contact plug. The nitride capping layer is disposed between the second contact plug and the conductive line.

A semiconductor device may include a substrate including an active pattern, a lower power line in a lower portion of the substrate, a channel pattern on the active pattern and including a plurality of semiconductor patterns, which are stacked and include a first semiconductor pattern at the lowermost level, a gate electrode crossing the active pattern and including a first inner gate electrode between the active pattern and the first semiconductor pattern, source/drain patterns on the substrate, backside contacts connecting the lower power line to the source/drain patterns, and a filler structure between adjacent backside contacts among the backside contacts. The filler structure may include a filling pattern and a liner. The filling pattern may include a contact portion on a filler portion, and the liner may cover opposite side surfaces of the filler portion. The contact portion may be in direct contact with the substrate.