A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

An example semiconductor device includes a lower wiring layer including lower wiring lines, an upper wiring layer including upper wiring lines, and a power gating cell between the lower and upper wiring layers. The power gating cell includes a first active region on a substrate and including first and second lower source/drain patterns and a first channel pattern connecting the first and second lower source/drain patterns with each other, a second active region on the first active region and including first and second upper source/drain patterns, and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to a top surface of the substrate. The lower wiring layer includes a global power line connected with the first lower source/drain pattern and a local power line connected with the second lower source/drain pattern.

In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

An integrated circuit device includes a channel region, a gate line surrounding the channel region, a source/drain region contacting the channel region, and a backside via contact passing through a portion of the source/drain region in a vertical direction from a back side of the source/drain region. The source/drain region includes a bottom epitaxial layer protruding from a bottom surface of the source/drain region, a blocking epitaxial layer contacting the channel region and the bottom epitaxial layer, and a main epitaxial layer filling a space defined by the blocking epitaxial layer. A first dopant concentration of the bottom epitaxial layer is greater than a second dopant concentration of the blocking epitaxial layer and is greater than or equal to a third dopant concentration of the main epitaxial layer, and the backside via contact passes through at least a portion of the bottom epitaxial layer in the vertical direction.

A method of forming backside contacts to source/drain (S/D) regions of a semiconductor structure includes removing a substrate selectively to shallow trench isolations (STIs) and the extension regions to form first recesses between the STIs, filling the first recesses with first dielectric material, forming second recesses aligned to the S/D regions through the first dielectric material, and forming backside contacts to the extension regions within the second recesses.

A method includes forming a first transistor over a substrate, in which the first transistor includes first source/drain epitaxy structures; forming a second transistor over the first transistor, in which the second transistor includes second source/drain epitaxy structures; forming an opening extending through one of the second source/drain epitaxy structures and exposing a top surface of one of the first source/drain epitaxy structures; performing a first deposition process to form a first metal in the opening, in which a first void is formed in the first metal during the first deposition process; performing a first etching back process to the first metal until the first void is absent; and performing a second deposition process to form a second metal in the opening and over the first metal.

A semiconductor device includes a back interlayer insulating film, a back wiring line within the back interlayer insulating film, a first source/drain pattern on the back wiring line, a second source/drain pattern on the back wiring line and spaced apart from the first source/drain pattern, and a back source/drain contact between the first source/drain pattern and the back wiring line, connected to the first source/drain pattern, and overlapping with the first source/drain pattern. The back source/drain contact is connected to the first source/drain pattern and, in a cross-sectional view cut perpendicular to a third direction, a first surface of the back source/drain contact has a convex shape, and in a cross-sectional view cut perpendicular to a second direction, the first surface of the back source/drain contact has a concave shape.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source/drain (S/D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S/D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S/D recesses by the nitride layers and form ILD recesses.

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source/drain region and a second source/drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source/drain region, and a second spacer layer below the second source/drain region, and a backside contact plug partially recessing a lower surface of the first source/drain region through the substrate insulating layer and the first spacer layer.

A method of manufacturing a semiconductor device comprises forming a preliminary substrate insulating layer on a lower substrate region; forming buried interconnection lines on the preliminary substrate insulating layer; forming a substrate insulating layer on the buried interconnection lines; forming an upper substrate region on the lower substrate region to form a substrate; forming active regions and a device isolation layer by removing a portion of the substrate; forming sacrificial gate structures and source/drain regions; removing the sacrificial gate structures; forming gate structures; forming a first interlayer insulating layer on the gate structures; forming first contact holes to expose the buried interconnection lines; forming preliminary lower contact plugs by filling the first contact holes; forming lower contact plugs; forming second contact holes to expose a portion of the source/drain regions or a portion of the gate structures; and forming upper contact plugs by filling the second contact holes.