A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed opposite the first and second device features from the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

A semiconductor device may include an insulating pattern on a first lower interlayer insulating layer, nanosheets vertically stacked on the insulating pattern, a gate electrode on the insulating pattern and surrounding the nanosheets, a source/drain region on one side of the gate electrode on the insulating pattern, and a source/drain contact electrically connected to the source/drain region. The source/drain region, the first lower interlayer insulating layer, and the insulating pattern may define a contact trench and the source/drain contact may fill the contact trench. The source/drain contact may include a barrier layer, a first filling layer between parts of the barrier layer in the contact trench, and a second filling layer in the contact trench under the first filling layer. The first filling layer may be multi grain and may have a first average grain size. The second filling layer may be single grain.

A device includes a channel layer, a gate structure, a first source/drain structure, a second source/drain structure, and a backside via. The gate structure surrounds the channel layer. The first source/drain structure and the second source/drain structure ate connected to the channel layer. The backside via is connected to a backside of the first source/drain structure. The backside via includes a first portion, a second portion, and a third portion. The first portion is connected to the backside of the first source/drain structure. The third portion tapers from the second portion to the first portion. A sidewall of the third portion is more inclined than a sidewall of the second portion.

Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.

A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

Provided is a semiconductor device which includes: a 1.sup.st field-effect transistor (FET) including a 1.sup.st source/drain pattern; a 2.sup.nd FET including a 2.sup.nd source/drain pattern, vertically above the 1.sup.st FET; a 1.sup.st side spacer on a right surface of the 1.sup.st source/drain pattern, the 1.sup.st side spacer comprising an isolation material; and a frontside contact structure on a right surface of the 2.sup.nd source/drain pattern and a right surface of the 1.sup.st side spacer, wherein the frontside contact structure is connected to the 2.sup.nd source/drain pattern and is isolated from the 1.sup.st source/drain pattern by the 1.sup.st side spacer.

Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.