Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

A chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a dielectric stack under the gate, the dielectric stack including one or more first dielectric layers and one or more second dielectric layers.

The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a trench isolation between a first source/drain region of a first transistor and a second source/drain region of a second transistor, wherein the trench isolation includes an upper portion and a lower portion; the lower portion has a first lower sidewall and a second lower sidewall that intersects with the first lower sidewall to form a pointy bottom of the trench isolation; a first lower conformal liner at the first lower sidewall and a second lower conformal liner at the second lower sidewall; and the first and second lower conformal liners pinch off at the pointy bottom. A method of forming the same is also provided.

Techniques are provided herein to form an integrated circuit having stacked semiconductor devices with their source or drain regions coupled together via matching backside connections. In an example, FET (field effect transistor) devices may be formed on two different substrates and bonded together at their backsides such that backside contacts beneath each device substantially align at or near the bonding interface. The substrate beneath both the first FET and the second FET is removed, and backside contacts are formed beneath the source or drain regions of the first and second FETs. A bonding layer may also be formed on the backside of either the first FET or the second FET. The second FET is then flipped upside down and bonded to the backside of the first FET, such that the backside contacts from the first and second FET's are substantially aligned and are conductively coupled through the bonding layer.

The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.

A semiconductor device includes a power transmission network layer on a first surface of a substrate, a source/drain pattern on the substrate, the source/drain pattern including a first pattern including a first material and a second pattern including a second material that is different from the first material, and a backside conductive contact that extends into the substrate and into the source/drain pattern. The backside conductive contact includes a first region that extends into the first pattern of the source/drain pattern and a second region on the first region. The second region of the backside conductive contact has a second width that is greater than a first width of the first region of the backside conductive contact in a direction parallel to a second surface of the substrate.

Techniques are provided herein to form an integrated circuit with a double-height standard cell layout that can utilize both frontside and backside connections. The layout involves merging two of the transistors into a single wider transistor that extends along the midline of the double-height standard cell layout. Accordingly, the double-height standard cell layout may include three total transistors with one transistor being wider than the other two. The transistors may be configured as an inverter with enhanced driving capability in the double height standard cell layout. The wider transistor at the center of the double-height standard cell layout includes a source or drain region with both a topside contact and a backside contact to provide additional interconnect routing flexibility. The double-height standard cell may include an n-channel device having a first width aligned along a centerline of the double-height standard cell and two p-channel devices or vice versa.