A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

An integrated circuit device includes: a fin-type active area extending in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active area; a source/drain area arranged on the fin-type active area; a gate dielectric layer disposed on the gate line; a source/drain contact arranged on the source/drain area; a via contact integrally connected to the source/drain contact and protruding in a vertical direction; a gate contact plug integrally connected to the gate line and protruding in the vertical direction; a first wiring layer electrically connected to the via contact and the gate contact plug; and a via rail connected to the first wiring layer, and extending in the first horizontal direction at a vertical level that is lower than a vertical level of the first wiring layer.

Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.

Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, an integrated circuit structure has layouts of differing brightness when exposed to an e-beam.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a method of fabricating a semiconductor structure comprises providing a FET structure disposed above a substrate, the FET structure comprising a vertical metal gate structure disposed between a pair of source/drain (S/D) epitaxial (EPI) structures and having a set of vertically-stacked, horizontal nanosheets extending through the vertical metal gate structure in the first horizontal direction to electrically connect the S/D EPI structures to each other. The method further comprises removing the substrate, removing the portion of vertical metal gate structure below the bottom-most nanosheet, removing at least enough of the bottom-most nanosheet to sever the its electrical conducting path between the S/D EPI structures, and filling the void created by the removed gate metal and nanosheet with a dielectric material that also covers the bottom surfaces of the S/D EPI structures.

A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

Disclosed is a semiconductor device including a substrate and a wiring structure on the substrate. The wiring structure includes a first interlayer dielectric layer on the substrate and including a plurality of first metal lines, and a second interlayer dielectric layer on the first interlayer dielectric layer and including a via structure connected to the first metal line. The via structure includes a first via part and a second via part on the first via part. A first width of the first via part is less than a second width of the second via part.

A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

A semiconductor device includes a dielectric layer, a p-type transistor over a first side of the dielectric layer, and an n-type transistor over a second side of the dielectric layer opposite to the first side of the dielectric layer. The p-type transistor includes a semiconductor channel layer, a first gate structure over the semiconductor channel layer, and source/drain epitaxy structures on opposite sides of the first gate structure. The n-type transistor includes a semiconductive oxide channel layer, a second gate structure over the semiconductive oxide channel layer, and source/drain contacts on opposite sides of the second gate structure.