A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

A method of modifying a dielectric film on a substrate includes depositing a protective polymer coating onto a dielectric film that covers top surfaces of fins and sidewalls and bottom of trenches in a substrate and forms a filled region at the bottom of the trenches, and plasma etching the substrate at processing conditions selected so as to remove the protective polymer coating and a portion dielectric film at the bottom of the trenches so as to increase the concavity of the top surface of the filled region.

A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a nanosheet stack including a plurality of nanosheets on the fin-type active region, a gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction intersecting with the first horizontal direction, and a vertical structure at least partially overlapping the gate line in the second horizontal direction and including a side wall in contact with each of the plurality of nanosheets. The vertical structure further includes a recessed portion on the side wall thereof.

Provided is a semiconductor device which includes: a 1.sup.st transistor including a 1.sup.st channel structure extended in a 1.sup.st direction, and a 1.sup.st gate structure on the 1.sup.st channel structure; a 2nd transistor comprising a 2.sup.nd channel structure extended in the 1.sup.st direction, and a 2.sup.nd gate structure on the 2.sup.nd channel structure, the 2.sup.nd transistor being disposed adjacent to the 1.sup.st transistor in a 2.sup.nd direction that horizontally intersects the 1.sup.st direction; a 1.sup.st isolation wall between the 1.sup.st channel structure and the 2.sup.nd channel structure; and a 1.sup.st gate cut structure between the 1.sup.st gate structure and the 2.sup.nd gate structure on the 1.sup.st isolation wall in a 3.sup.rd direction that vertically intersects the 1.sup.st direction and the 2.sup.nd direction.

Systems, methods, and apparatus are provided for bifurcated access line contacts. Horizontally oriented access devices each have a first source/drain region and a second source drain region separated by channel regions. Gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from channel regions by gate dielectrics. Horizontally oriented storage nodes can be electrically coupled to the second source/drain regions of the horizontally oriented access devices. A staircase structure at each level on a periphery of the array of vertically stacked memory cells and a plurality of separate vertical connections each connected to a different one of a plurality of horizontally oriented access lines formed with the GAA structures on each level of the array.