A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

A semiconductor structure and a method for forming the same, where the semiconductor structure includes a substrate; a channel layer structure suspended above the substrate, where in the vertical direction, the channel layer structure includes one or more spaced channel layers; a repair layer covering the surfaces of the channel layers; and a gate structure located on the substrate and spanning the channel layer structure, where the gate structure surrounds the channel layers along the extension direction of the gate structure and covers the repair layer.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.

In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.

A method for forming an integrated circuit device, the method comprising: forming a stack of field effect transistors, FETs, comprising a bottom FET and a top FET; forming a first trench underneath the bottom FET; forming a first hole, between the first trench and a first source/drain region of the bottom FET; forming a second hole, between the first hole and a contact of a contact layer arranged above the top FET; performing a first metal deposition to fill the first hole; the second hole; and part of the first trench, with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer below the recessed metal; performing a second metal deposition to fill the first trench with metal, thereby forming a first backside wiring line in the first trench.

A method includes forming a gate stack over a semiconductor region, etching the semiconductor region to form a source/drain recess aside of the gate stack, depositing a first dielectric layer, wherein a portion of the first dielectric layer is in the source/drain recess, performing a treatment process on the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, and etching the second dielectric layer and the first dielectric layer. A first portion of the first dielectric layer and a second portion of the second dielectric layer remain at a bottom of the source/drain recess to form a dielectric region. A source/drain region is deposited in the source/drain recess and over the dielectric region.

A semiconductor device may include a semiconductor substrate including first and second regions, a first gate structure on the first region, and a second gate structure on the second region. Each of the first and second gate structures may include a metal pattern, a high-k dielectric pattern between the semiconductor substrate and the metal pattern, and a work-function layer between the high-k dielectric pattern and the metal pattern. The work-function layer of the first gate structure may include a first metal element in the metal pattern of the first gate structure and a dipole material in the high-k dielectric pattern of the first gate structure, and the work-function layer and the high-k dielectric pattern in the second gate structure may include a metal oxide material. In the second gate structure, an oxygen content in the work-function layer may be higher than that in the high-k dielectric pattern.