Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure, wherein each transistor structure includes at least one channel region; depositing a work function material over the first transistor structure and the second transistor structure; and selectively removing the work function material from the first transistor structure while maintaining the work function material over the second transistor structure using a masked etching process, wherein after the selectively removing, the first transistor structure is free of the work function material and the second transistor structure retains the work function material.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

A semiconductor device structure is described. The structure includes a fin structure formed on a substrate, a source/drain feature disposed adjacent the fin structure and over the substrate, wherein a top surface of the source/drain feature and a front side of the substrate are substantially co-planar, an isolation trench extending from the front side of the substrate towards a backside of the substrate, and a backside via contact extending from the backside of the substrate towards and in contact with the source/drain feature, wherein the backside via contact and the isolation trench are parallelly arranged and separated from each other by a constant gap along boundaries of the backside via contact and the isolation trench.

Disclosed herein are methods, devices and systems including a substrate, a transistor channel on the substrate and extending in direction parallel to the substrate, a first electrode extending in a direction orthogonal to the substrate and coupled to the transistor channel, a second electrode coupled to the transistor channel and extending in a direction orthogonal to the substrate and parallel to the first electrode, and a first epitaxial structure arranged between the transistor channel and the first electrode. The first epitaxial structure may share a common crystalline orientation with the transistor channel, and may separate a surface of the first electrode and a surface of the transistor channel in a direction parallel to the substrate by a distance varying along the length of the first electrode.

Various embodiments of the disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first dielectric wall disposed over a substrate, and a first metal gate structure portion and a second metal gate structure portion disposed on opposing sides of the first dielectric wall, each comprising a plurality of semiconductor layers vertically stacked and separated from each other; a high-k dielectric layer surrounding at least three surfaces of each semiconductor layer, a gate electrode layer disposed between adjacent semiconductor layers, and a second dielectric wall disposed adjacent to the first metal gate structure portion, the second dielectric wall having a top surface at an elevation lower than a top surface of the first dielectric wall, and a metal layer disposed over the second dielectric wall and in contact with the gate electrode layer of the first and second metal gate structure portions.

A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.

An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.

A semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. The first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. The dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. The first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.

The present disclosure describes a semiconductor device having an identification device for chip identification. The semiconductor structure includes first and second channel structures on a substrate, a gate structure on the first and second channel structures, an epitaxial structure on the first and second channel structures, and a first source/drain (S/D) contact structure on the first channel structure. The epitaxial structure is at a first side of the gate structure and the first S/D contact structure is at a second side of the gate structure opposite to the first side. The semiconductor structure further includes a second S/D contact structure on the second channel structure. The second S/D contact structure is at the second side of the gate structure.

Some implementations described herein provide techniques and semiconductor devices in which a buffer region is formed under a source/drain region of a device. The buffer region is configured to reduce, prevent, and/or block migration of dopants from the source/drain region to other areas of the device, such a mesa region of an adjacent fin structure. In some implementations, a sidewall layer is between the buffer region and the mesa region. Additionally, or alternatively, a dielectric region including a dielectric gas may be between the buffer region and the source/drain region.